Motorola DSP56367 User Manual page 456

24-bit digital signal processor
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Programmer's Reference
Application:
HOST (HDI08)
Receive Request Enable
DMA Off
DMA On
Transmit Request Enable
DMA Off
DMA On
HDRQ
HOREQ/HTRQ
0
HOREQ
1
HTRQ
Host Flags
Write Only
Host Little Endian
Initialize (Write Only)
0 = No Action
For HM[1:0] bits, see
Table 6-12 in Section 6
Receive Data Register Full
0 = Wait
Transmit Data Register Empty
0 = Wait
Transmitter Ready
0 = Data in HI
Host Flags
Read Only
Host Request
0 = HOREQ Deasserted
Figure D-9 Host Interrupt Control and Interrupt Status
D-24
Processor Side
0 = Interrupts Disabled
1 = Interrupts Enabled
0 = Host -> DSP
1 = DSP -> Host
0 = Interrupts Disabled
1 = Interrupts Enabled
0 = DSP -> Host
1 = Host -> DSP
HACK/HRRQ
HACK
HRRQ
1 = Initialize DMA
HDM[2:0] = 000
HDM[2:0] = 100
HDM1 and/or HDM0 = 1
Interrupt Control Register (ICR)
1 = Read
1 = Write
1 = Data Not in HI
1 = HOREQ Asserted
Interrupt Status Register (ISR)
DSP56367
Date:
Programmer:
7
6
5
INIT
HLEND
* 0
HM1
HM0
INIT
INIT
(HDM1)
(HDM0) HF1
$0 R/W
Reset = $0
7
6
5
*
0
*
HREQ
0
$2 R/W
Reset = $0
*
= Reserved, Program as 0
Sheet 4 of 6
4
3
2
1
0
HF1
HF0
HDRQ
TREQ
RREQ
HF1
TREQ
RREQ
* 0
HF0
HF0
TREQ
RREQ
* 0
4
3
2
1
0
HF3
HF2
TRDY
TXDE
RXDF
MOTOROLA

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