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interrupt acknowledge input. If HDM[2:0] are not all cleared, the HDI08 operates as
described in Table 8-5.
HDM
2
1
0
Description
0
0
0
DMA operation disabled
1
0
0
DMA Operation Enabled.
Host may set HM1 or HM0 in
the ICR to enable DMA
transfers.
0
0
1
DMA Mode Data Output
Transfers Enabled.
(24-Bit words)
0
1
0
DMA Mode Data Output
Transfers Enabled.
(16-Bit words)
0
1
1
DMA Mode Data Output
Transfers Enabled.
(8-Bit words)
1
0
1
DMA Mode Data Input
Transfers Enabled.
(24-Bit words)
1
1
0
DMA Mode Data Input
Transfers Enabled.
(16-Bit words)
1
1
1
DMA Mode Data Input
Transfers Enabled.
(8-Bit words)
If HDM1 or HDM0 are set, the DMA mode is enabled, and the HOREQ signal is used to
request DMA transfers (the value of the HM1, HM0, HLEND and HDREQ bits in the ICR
have no affect). When the DMA mode is enabled, the HDM2 bit selects the direction of DMA
transfers:
– setting HDM2 sets the direction of DMA transfer to be DSP to host and enables
the HOREQ signal to request data transfer.
– clearing HDM2 sets the direction of DMA transfer to be host to DSP and enables
the HOREQ signal to request data transfer.
The HACK input signal is used as a DMA transfer acknowledge input. If the DMA direction
is from DSP to host, the contents of the selected register are driven onto the host data bus
MOTOROLA
Table 8-5 HDM[2:0] Functionality
INIT
INIT
HM1
INIT
HDM1 HDM0
DSP56367
Host Interface (HDI08)
HDI08 – DSP-Side Programmer's Model
Mode
ICR
HLEND
HF1
HF0
HDRQ TREQ
HM0
HF1
HF0
HF1
HF0
RREQ
TREQ
RREQ
TREQ
RREQ
8-9
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