Audio Data Register Empty Interrupt Handling - Motorola DSP56367 User Manual

5. Enable DAX by setting PC1 bit (and by setting PC0 bit if in slave mode) in the port
control register (PCR); transmission begins.
12.6.2

AUDIO DATA REGISTER EMPTY INTERRUPT HANDLING

When the XDIE bit is set and the DAX is active, an audio data register empty interrupt
(XADE = 1) is generated once at the beginning of every frame transmission. Typically, within
an XADE interrupt, the non-audio data bits of the next frame are stored in XNADR and one
frame of audio data to be transmitted in the next frame is stored in the FIFO by two
consecutive MOVEP instructions to XADR. If the non-audio bits are not changed from frame
to frame, this procedure can be handled within a fast interrupt routine. Storing the next
frame's audio data in the FIFO clears the XADE bit in the XSTR.
12.6.3 BLOCK TRANSFERRED INTERRUPT HANDLING
An interrupt with the XBLK vector indicates the end of a block transmission and may require
some computation to provide the next non-audio data structures that are to be transmitted
within the next block. Within the routine, the next audio data can be stored in the FIFO by two
consecutive MOVEP instructions to XADR, and the next non-audio data can be stored in the
XNADR. The XBLK interrupt occurs only if the XBIE bit in XCTR is set. If XBIE is cleared,
a XADE interrupt vector will take place.
12.6.4 DAX OPERATION WITH DMA
During DMA transfers, the XDIE bit of the XCTR must be cleared to avoid XADE interrupt
services by the DSP core. The initialization appearing in Section 12.6.1 is relevant for DMA
MOTOROLA
DAX Programming Considerations
DSP56367
Digital Audio Transmitter
12-13