Tccr Transmit Prescale Modulus Select (Tpm7–Tpm0) - Bits 0–7 - Motorola DSP56367 User Manual

Enhanced Serial Audio Interface (ESAI)
ESAI Programming Model
mode (SYN=1), the bit clock defined for the transmitter determines the receiver bit clock as
well. TCCR also controls the number of words per frame for the serial data.
11
X:$FFFFB6 TDC2
23
THCKD TFSD TCKD THCKP TFSP
Hardware and software reset clear all the bits of the TCCR register.
The TCCR control bits are described in the following paragraphs.
10.3.1.1 TCCR Transmit Prescale Modulus Select (TPM7–TPM0) - Bits 0–7
The TPM7–TPM0 bits specify the divide ratio of the prescale divider in the ESAI transmitter
clock generator. A divide ratio from 1 to 256 (TPM[7:0]=$00 to $FF) may be selected. The bit
clock output is available at the transmit serial bit clock (SCKT) pin of the DSP. The bit clock
output is also available internally for use as the bit clock to shift the transmit and receive shift
registers. The ESAI transmit clock generator functional diagram is shown in Figure 10-3.
10-10
10 9 8 7
TDC1 TDC0 TPSR TPM7
22 21 20 19
Figure 10-2 TCCR Register
DSP56367
6 5 4 3
TPM6 TPM5 TPM4 TPM3
18 17 16 15
TCKP TFP3 TFP2 TFP1
2 1 0
TPM2 TPM1 TPM0
14 13 12
TFP0 TDC4 TDC3
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