Pll Performance Issues - Motorola DSP56367 User Manual

• Minimize the capacitive load on the pins.
• Connect the unused inputs to pull-up or pull-down resistors.
• Disable unused peripherals.
One way to evaluate power consumption is to use a current per MIPS measurement
methodology to minimize specific board effects (i.e., to compensate for measured board
current not caused by the DSP). A benchmark power consumption test algorithm is listed in
Appendix E on page E-1. Use the test algorithm, specific test current measurements, and the
following equation to derive the current per MIPS value.
⁄
I MIPS = I MHz
where :
F2)
Note: F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1
could be 33 MHz. The degree of difference between F1 and F2 determines the
amount of precision with which the current rating can be determined for an
application.
4.4

PLL PERFORMANCE ISSUES

The following explanations should be considered as general observations on expected PLL
behavior. There is no testing that verifies these exact numbers. These observations were
measured on a limited number of parts and were not verified over the entire temperature and
voltage ranges.
4.4.1 INPUT (EXTAL) JITTER REQUIREMENTS
The allowed jitter on the frequency of EXTAL is 0.5%. If the rate of change of the frequency
of EXTAL is slow (i.e., it does not jump between the minimum and maximum values in one
cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a long
time), then the allowed jitter can be 2%. The phase and frequency jitter performance results
are only valid if the input jitter is less than the prescribed values.
MOTOROLA
⁄ ( ) ⁄ (
= I – I F2 F1
typF2 typF1
I = current at F2
typF2
I = current at F1
typF1
F2 = high frequency (any specified operating frequency)
F1 = low frequency (any specified operating frequency lower than
DSP56367
)
–
Design Considerations
PLL Performance Issues
4-5