Isr Receive Data Register Full (Rxdf) Bit 0 - Motorola DSP56367 User Manual

Host Interface (HDI08)
HDI08 – External Host Programmer's Model
registers by stepping through the HDI08 addresses. The ISR cannot be accessed by the DSP
core. The ISR bits are described in the following paragraphs.
Figure 8-14 Interface Status Register (ISR)
7 6
HREQ
- Reserved bit. Read as 0. Should be written with 0 for future compatibility.
8.6.3.1

ISR Receive Data Register Full (RXDF) Bit 0

The RXDF bit indicates that the receive byte registers (RXH:RXM:RXL) contain data from
the DSP core and may be read by the host processor. RXDF is set when the contents of HOTX
is transferred to the receive byte registers. RXDF is cleared when the receive data (RXL or
RXH according to HLEND bit) register is read by the host processor. RXDF can be cleared by
the host processor using the initialize function. RXDF may be used to assert the external
HOREQ signal if the RREQ bit is set. Regardless of whether the RXDF interrupt is enabled,
RXDF indicates whether the RX registers are full and data can be latched out (so that polling
techniques may be used by the host processor).
8.6.3.2 ISR Transmit Data Register Empty (TXDE) Bit 1
The TXDE bit indicates that the transmit byte registers (TXH:TXM:TXL) are empty and can
be written by the host processor. TXDE is set when the contents of the transmit byte registers
are transferred to the HORX register. TXDE is cleared when the transmit (TXL or TXH
according to HLEND bit) register is written by the host processor. TXDE can be set by the
host processor using the initialize feature. TXDE may be used to assert the external HOREQ
signal if the TREQ bit is set. Regardless of whether the TXDE interrupt is enabled, TXDE
indicates whether the TX registers are full and data can be latched in (so that polling
techniques may be used by the host processor).
8.6.3.3 ISR Transmitter Ready (TRDY) Bit 2
The TRDY status bit indicates that TXH:TXM:TXL and the HORX registers are empty.
If TRDY is set, the data that the host processor writes to TXH:TXM:TXL is immediately
transferred to the DSP side of the HDI08. This feature has many applications. For example, if
the host processor issues a host command which causes the DSP core to read the HORX, the
host processor can be guaranteed that the data it just transferred to the HDI08 is what is being
received by the DSP core.
8.6.3.4 ISR Host Flag 2 (HF2) Bit 3
The HF2 bit in the ISR indicates the state of host flag 2 in the HCR on the DSP side. HF2 can
be changed only by the DSP (see Section 8.5.3.4).
8-26
5 4
HF3
•
TRDY=TXDE
DSP56367
3 2
HF2 TRDY
HRDF
1 0
TXDE RXDF
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