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Host Interface (HDI08)
HDI08 – DSP-Side Programmer's Model
when HACK is asserted. If the DMA direction is from host to DSP, the selected register is
written from the host data bus when HACK is asserted.
The size of the DMA word to be transferred is determined by the DMA control bits,
HDM[1:0]. Only the data registers TXH, TXM, TXL and RXH, RXM, RXL can be accessed
in DMA mode.The HDI08 data register selected during a DMA transfer is determined by a
2-bit address counter, which is preloaded with the value in HDM[1:0]. The address counter
substitutes for the address bits of the HDI08 during a DMA transfer. The address counter can
be initialized with the INIT bit feature. After each DMA transfer on the host data bus, the
address counter is incremented to the next register. When the address counter reaches the
highest register (RXL or TXL), the address counter is not incremented but is loaded with the
value in HDM[1:0]. This allows 8-, 16- or 24-bit data to be transferred in a circular fashion
and eliminates the need for the DMA controller to supply the HA2, HA1, and HA0 signals.
For 16- or 24-bit data transfers, the DSP CPU interrupt rate is reduced by a factor of 2 or 3,
respectively, from the host request rate – i.e., for every two or three host processor data
transfers of one byte each, there is only one 24-bit DSP CPU interrupt.
If HDM1 or HDM0 are set, the HM[1:0] bits in the ICR register reflect the value of
HDM[1:0].
The HDM[2:0] bits should be changed only while HEN is cleared in the HPCR.
8.5.3.6
HCR Reserved Bits 8-15
These bits are reserved. They read as zero and should be written with zero for future
compatibility.
8.5.4
HOST STATUS REGISTER (HSR)
The HSR is a 16-bit read-only status register used by the DSP to read the status and flags of
the HDI08. It cannot be directly accessed by the host processor. The initialization values for
the HSR bits are described in Section 8.5.9. The HSR bits are described in the following
paragraphs.
Figure 8-3 Host Status Register (HSR) (X:FFFFC3)
15
14
13
12
- Reserved bit. Read as 0. Should be written with 0 for future compatibility.
8.5.4.1
HSR Host Receive Data Full (HRDF) Bit 0
The HRDF bit indicates that the host receive data register (HORX) contains data from the host
processor. HRDF is set when data is transferred from the TXH:TXM:TXL registers to the
HORX register. HRDF is cleared when HORX is read by the DSP core. If HRDF is set the
8-10
11
10
9
8
DSP56367
7
6
5
4
DMA
HF1
3
2
1
0
HF0
HCP
HTDE HRDF
MOTOROLA
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