Motorola DSP56367 User Manual page 174

Core Configuration
Interrupt Priority Registers
11 10 9
ESL10 TAL1
ESL11
23 22 21
Reserved bit. Read as zero, should be written with zero for future compatibility.
11 10 9
IDL2 IDL1 IDL0
22
23 21
D5L1 D5L0 D4L1
6-8
7 6 5
8
TAL0 DAL1 DAL0 HDL1
20 19 18 17
Figure 6-1 Interrupt Priority Register P
7 6 5
8
ICL2 ICL1 ICL0 IBL2
20 19 18 17
D4L0 D3L1 D3L0 D2L1
Figure 6-2 Interrupt Priority Register C
DSP56367
4 3 2 1
HDL0 SHL1 SHL0 ESL1
16 15 14 13
4 3 2 1
IBL1 IBL0 IAL2 IAL1
16 15 14 13
D2L0 D1L1 D1L0 D0L1
0
ESL0
ESAI IPL
SHI IPL
HDI08 IPL
DAX IPL
TRIPLE TIMER IPL
ESAI_1 IPL
12
reserved
0
IAL0
IRQA IPL
IRQA mode
IRQB IPL
IRQB mode
IRQC IPL
IRQC mode
IRQD IPL
IRQD mode
12
D0L0
DMA0 IPL
DMA1 IPL
DMA2 IPL
DMA3 IPL
DMA4 IPL
DMA5 IPL
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