Mitsubishi Electric MELSEC-Q00U(J)CPU User Manual page 480

(a) When the latch interval is set to "Each Scan"
The processing time listed in the following table is required.
Q00UJCPU, Q00UCPU, Q01UCPU
Q02UCPU
Q03UD(E)CPU
Q03UDVCPU
Q04UD(E)HCPU, Q06UD(E)HCPU, Q10UD(E)HCPU, Q13UD(E)HCPU,
Q20UD(E)HCPU, Q26UD(E)HCPU, Q50UDEHCPU, Q100UDEHCPU
Q04UDVCPU, Q04UDPVCPU, Q06UDVCPU, Q06UDPVCPU, Q13UDVCPU,
Q13UDPVCPU, Q26UDVCPU, Q26UDPVCPU
*1 When setting the latch range of the timer (T), retentive timer (ST), and counter (C), one point for word device and two
points for bit device are occupied per point.
*2 The case where the points are set for the latch relay (L) is included.
*3 The scan time will not increase if the latch range is set for the file register (ZR), extended data register (D), or extended
link register (W).
(b) When the latch interval is set to "Time Setting"
The processing time listed in the following table is required. The scan time including the first END processing
after a preset time has elapsed increases.
Q03UDVCPU, Q04UDVCPU, Q04UDPVCPU, Q06UDVCPU, Q06UDPVCPU,
Q13UDVCPU, Q13UDPVCPU, Q26UDVCPU, Q26UDPVCPU
To reduce the scan time increase due to latch
latch relay) as much as possible by performing the following.
• Move data to be latched to the file register.
• Store device data that is less frequently updated in the standard ROM with the SP.DEVST instruction. (The device
data stored in the standard ROM can be read with the S(P).DEVLD instruction. (
• Set the latch interval to "Time Setting". (
*1 For file registers (including an extended data register (D) and an extended link register (W)), the scan time is not
increased due to latch.
478
CPU module
CPU module
*1
, minimize the number of latch points (latch (1) setting, latch (2) setting, and
(4.4 × N1) + (0.12 × (N2  16 + N3))µs
(4.0 × N1) + (0.12 × (N2  16 + N3))µs
(3.0 × N1) + (0.12 × (N2  16 + N3))µs
(1.0 × N1) + (0.085 × (N2  16 + N3)) + 1.2µs
(3.0 × N1) + (0.05 × (N2  16 + N3))µs
(1.0 × N1) + (0.045 × (N2  16 + N3)) + 1.2µs
(1.0 × N1) + (0.004 × (N2  16 + N3)) + 17.5µs
Page 124, Section 3.3 (5) (b))
Processing time
Processing time
Page 258, Section 3.30)