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a signal from the delay line, thus controlling the output pulse width.
Output pulse widths
may be increased by performing an OR function at the inputs to the timing amplifiers on the
CM-003.
The reset output of the CM-003 flip-flop is used to generate a memory-busy indi-
cation during the fir st portion of a memory cycle.
Timing pulses generated by the CM-003 are used to (1) enable X- and Y- switches
and sinks, (2) time the selection of X- and Y- switches and sinks, (3) generate a strobe pulse
for the sense amplifiers, and (4) initiate a similar series of pulses at the write timing dis-
tributor.
No strobe pulse is generated by the write timing distributor.
The strobe pulses {STRBl +X) sample the core signal during the read portion of the
cycle.
The sampling interval is chosen for appropriate signal and noise conditions.
The read CM-003 generates a read pulse on the ENSKl+ outputs, enabling the X-
and Y- current sinks selected by the decoded addre1:>1:>.
The selected X- and Y - switches are
then enabled by the ENYSW + signal.
The read-write interchange is implemented by gating
the YlOXX input with RYSW+, RSKAl+, WYSWA+ and WSKAl+.
YSWRL+ or YSWRH+ are
never true simultaneously (if one is a read pulse, the other must be a write pulse).
Both
signals turn on Y- switch currents.
Similarly, Y- sink activate pulses YSKRL+ and YSKRH+
are generated by interchanging RSKAl + and WSKAl + as a function of Y l OXX.
Regeneration Loop
A block diagram of the regeneration loop for bit 1 is shown in Figure 2-29.
If
a read
operation is to be performed, the M-register in the CPU is reset within 330 ns after the
start of a cycle.
During the write portion of every cycle, input data will be available from
the M-register no later than 600 ns after the cycle is initiated.
When a read operation is
performed, the M-register is set if the sense amplifier output is activated (0 volt= ONE).
There is one sense amplifier for every 4, 096 cores.
A bit read out of the core stack
will be sensed by one of the sense amplifiers.
The amplifier outputs are ORed together so
that an output from either amplifier will set the corresponding M-register stage.
The M-
register output is gated with the read data timing signal {RDATA-).
When the register is a
ONE, the write Y - switch is turned on and the addressed core is switched to a ONE state.
If the core output is a ZERO, the register remains reset, write Y - drive current does not
flow and the selected core remains in the ZERO state.
The CM-032 f.L-PAC (see Appendix for complete description) is used for the sense
amplifier and cable driver in an
BK
memory.
A 4K memory uses CM-033 f.L-PACs, which
are the same as the CM-032 except that only one sense amplifier per bit is used.
Memory Retention
The magnetic core array does not require power to provide its static memory
capability.
A pulse of power is required to switch cores from one state to the other.
How-
ever, the pulse is not necessary to hold cores in their respective states.
Because of the
retentivity of the core magnetic material, the cores will remain in the state to which they
have been switched.
If power is removed, or lost, the magnetic core array will retain
stored information indefinitely.
2-43
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