Table of Contents
Advertisement
Control Inputs Used to Steer Clock Pulses
If both the set controls (SC) and the reset controls (RC) are logic ONES, the flip-
flop will be complemented by the application of a clock pulse.
If
only SC or RC is a ONE,
the state of the flip-flop will be a ONE or ZERO, respectively, after the clock is energized.
If both SC and RC are ZERO, the flip-flop will remain in its previous state.
One restric-
tion is that when a control input is used to gate the clock, the control input cannot change
from the ONE to the ZERO state while the clock is a ONE.
Figure A-11 contains diagrams
and equations describing this mode of flip-flop operation.
A) LOGIC
DIAGRAM
SET
OUTPUT
SET
(
•1
CONTROL
•2
CLOCK
(
r I
RESET
CONTROL
r
2
ALL DC
INPUTS
B) Truth Table and Boolean Equations
SC - AND result of the set control inputs,
RC - AND result of the reset control inputs,
F' - previous state of the flip-flop
SET
AND RESET
MUST BE
LOGIC ONES.
SC
=
s 1 • s 2
Re=
rl. r2
F
-
state of the flip-flop after the clock pulse
s
R
F
F
0
0
0
0
NO CHANGE
0
0
I
I
0
I
0
0
RESET
0
I
I
0
I
0
0
I
SET
I
0
I
I
I
I
0
I
COMPLEMENT
I
I
I
0
Figure A-11.
Control Inputs Used to Gate Clock Pulses (Sheet 1
of
2)
A-17
Advertisement
Table of Contents
