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A-6
c;;
0
z
0
CJ
l&J
(/)
0
,,-;-....
z
>- ~
ct ct
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z
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l&J
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l&J 0
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ct ct w
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m
en
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z
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w
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541
36
3~
32
30
28
26
24
zz
20
18
TYPICAL CIRCUIT DELAY OF NANO GATES
SYSTEM OPERATING
AMBIENT
:oO
C
8 LOADS
I ACTIVE
Vee= +6VOLTS
5 LOADS
3 LOADS
I ACTIVE
I ACTIVE
16
'-----~,----------------...-----~,-----.-----...-----
.....
0
10
20
30
40
50
60
70
80
BACK PLANE WIRING CAPACITANCE
(pf)
Figure A-2.
Typical NAND Gate Circuit Delays (Sheet 1 of 3)
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