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PARALLEL TRANSFER GA TE PAC, MODEL GM-022
GENERAL DESCRIPTION
The Parallel Transfer Gate PAC, Model CM-022 (Figure A-68), utilizes seven
F-01 dual NAND gate microcircuits containing fourteen 2-input NAND gates without collec-
tor resistors.
These circuits provide a facility for connecting the NAND gates in parallel
without decreasing the output drive capability.
The PAC can be used for the common transfer control of up to fourteen data sig-
nals.
The data when transferred is inverted in polarity.
CIRCUIT FUNCTION
The NAND gates are arranged in four independent groups.
Two of the groups
contain four NAND gates each, one input being common to the four gates.
The remaining
two groups contain three NAND gates each, one input being common to the three gates.
Each gate performs the NAND function with conventional positive logic (+6v
=
ONE, Ov
=
ZERO).
When both inputs are at passive or open, the output transistor is turned
on, and the output is active (ground). If any input is at ground, the transistor is turned off,
and the output is passive (the supply voltage, +6v).
The four common inputs can be externally connected to transfer a maximum of
14 bits of data simultaneously.
With this arrangement, the data to be transferred is con-
nected to the individual input of each gate and a strobe input is applied to the common input.
SPECIFICATIONS
Ref.
De sig.
Ml - M7
Cl
Frequency of Operation
DC to 5 me
Input Loading
Individual inputs:
1 unit load each
Common inputs:
1 unit load per gate
MICROCIRCUIT:
Output Drive Capability
8 unit loads
Circuit Delay (measured at + 1. 5v averaged
over two stages)
30 ns (max)
Current Requirements
+ 6v:
95 ma (max)
Power Dissipation
560 mw (max)
Electrical Parts List
Description
3C Part No.
950 100 001
F-01, dual NAND gate integrated circuit
CAPACITOR, FIXED, PLASTIC DIELECTRIC:
930 313 016
0. 033 µf ±20%, 50 vdc
A-119
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