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+v
- - - - +l.5VOLTS
I
------------'
- -
- -
0 VOLTS
I
•I
Tl
(POSITIVE TIME)
=
40 NSEC. (MIN)
T
2
(NEGATIVE TIME)
=
60 NSEC. (MIN)
+V
(INPUT ONE LEVEL)
=
+3.0 VOLTS (MIN)
T RISE AND T FALL REQUIREMENT - ANY µ-PAC OUTPUT SIGNAL WILL
HIA
RELIABLY TRIGGER THE FLIP-FLOP.
Figure A-14.
Flip-Flop Input Pulse Requirements
I
I
I
\l~--~'---Y------
~
+-------
TI
(TIME AT LOGIC ZERO)
=
8 0 NSEC. (MIN.)
V
(INPUT ONE LEVEL)
=
+3.0 VOLTS (MIN.)
+v
+1.5 VOLTS
0 VOLTS
A511
Figure A-15.
DC Set and Reset Input Signal Requirements
Maximum Allowable Clock Skew
In cases where a register is being driven by clock (shift) signals from different
sources, the output of one stage may arrive at the next stage before late clock signal.
If the
delay between the early and late clock signals is more than 3 0 nsec, erroneous data transfer
may occur.
To guarantee proper operation the allowable clock skew must be as shown in
Figure A-1 7.
Note that the triggering signal to flip-flop B is SA rather than CB.
This
situation is not detrimental to the operation of the shift register.
Either SA or CB may
trigger flip-flop B, depending on which occurs first.
A-22
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