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and all other cores linked by 01Y1 and or Xl are subjected to half-currents.
Consequently,
a unique core address can be selected Ly energizing an X- drive line and one Y- drive line
per bit.
Consider a read operation with all cores in array one (bit 1) in the counterclock-
wise magnetic state (ZERO) and all cores in array five (bit 5) in the ONE state.
Assume
that IY + drive currents flow in lines 01Y1 and 05Y1 and IXR current flows in line X 1.
Core
c
1
11+ is switched to the ZERO state and the resultant flux change appears as a differential
voltage at the sense winding terminals (SWOl ).
This voltage is amplified, strobed, and
standardized, setting the corresponding M-register stage to a ONE.
If the direction of the
Y- drive current is reversed (IY-), core
c
1
11- will be switched.
Core
c
5
11+ was in the
ZERO state so the currents drive the core further into saturation.
This results in a flux
change too small to be recognized by the sense amplifier.
Core C
5
11- is subjected to a net
field of ZERO.
After the read operation, both cores at the selected address have been interrogated
and the stored information has been transmitted to the central processor.
Since the readout
was destructive, the previously stored information must be reinserted during the write por-
tion of the cycle.
The M-register in the CPU pr es ents the data to be restored in memory.
This data, which is transmitted to the memory on lines MXXXX-, controls the Y - drive
currents.
Bit-1 currents flow, but there is no current in 05Yl because the bit-5 data input
is in the ZERO state.
The result is that core C
1
11 + is switched to the ONE and core C
5
11+
remains in the ZERO state.
All other cores remain in their original state.
ADDRESSING AND SELECTION
Address Inputs
Twenty-seven address lines control the memory selection circuits.
These lines
are described in the following paragraphs.
Thirteen address input lines (Y04XX+ through Yl6XX+) provide the memory with
the true binary coded address to be accessed.
The address input complements (Y04XX-
through Yl6XX-) are also provided.
One additional line (BANKX-) from the CPU will, when
at O volt, select its associated memory module.
When the BANKX- line attached to a given
memory is at +6 volts, the digit drivers in that module are disabled.
In addition, although
the X-drivers turn on, and the timing is generated as in normal operation, core states
within the module remain unchanged.
Decoding and Selection
A simplified diagram of address decoding and selection for a typical bit (bit 1) of
an 8K memory is given in Figure 2-27.
Each address line shown represents a binary bit.
Four bits are transferred to the X- switches and four to the X- sinks.
The X- switches
uniquely enable one of 16 read/write output pairs going to the X- diode matrix.
The X-
sinks select one of 16 read/write buses, and the selected bus enables one of 16 drive lines.
2-36
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