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Current Requirements
Current requirements are listed in the specifications for each individual µ-PAC.
The requirements are calculated on a nominal worst-case basis, in which the circuit inputs
are assumed to be in the condition capable of causing the maximum current drain for a
particular voltage.
The nominal worst-case is selected instead of the extreme worst- case
to provide a more realistic figure for power requirements and therefore permit more equip-
ment to be driven by a power supply.
Since it is very unlikely that all gates in a system
would be on at the same time, the nominal worst-case calculations provide a considerable
safety factor.
The current specifications include only the current used in the specific µ-PAC and
do not include the current going to external loads.
Since the input load current is included in
the specification, total system current requirements can be calculated by adding the rated
currents for all µ-PACs in the system.
Worst Case Delays
Worst- case delays are specified over the full temperature range and under loading
conditions which result in the longest propagation delay.
(Eight de gate loads are assumed
for turn-on and one active de gate load is assumed for turn-off.) For a gating circuit, the
delay is specified as the average of the turn-on and turn-off delays.
The total capacitance
driven under the specified worst-case condition is 1 5 pf of wiring capacitance plus the
capacitance accumulated in a µ-BLOC system when driving eight unit loads.
This capacitance
may be present during turn-off as well as turn-on, since it is possible to fan out to eight unit
loads and yet have only one gate active.
(The other seven loads may be inhibited by inputs
at ground.) The effect of additional wiring capacitance on gate delays is discussed under
Typical Delay Character is tics.
The preceding conditions apply to all gate and flip-flop circuits.
Power amplifier
delay specifications assume the condition of driving 25 active de gate loads plus a total of
250 pf of capacitance.
Typical Delay Characteristics
The curves in Figure A-2 show typical circuit delays of the basic NAND gate,
plotted against variations in temperature, sys tern wiring capacitance, and de and capaci-
tive loading conditions.
For example, the "5 loads, 1 active" curve shows the delay char-
acteristic of a gate output that fans out to five gates, four of which are inhibited by logic
ZERO signals on other inputs.
Connector, printed circuit, and input capacitance when
fanning out to 5 unit loads are taken into consideration.
The worst-case condition is also
plotted.
This is the
11
8 loads, 1 active" curve, where 1 active load is being driven from an
output that fans out to 8 unit loads.
In this situation, the maximum stray capacitance is
being driven by the minimum charging current, resulting in longer turn-off delays.
Although the curves are plotted beyond 40 picofarads of additional wiring capaci-
tance, that amount of wiring capacitance is unlikely to appear on any output in a µ-BLOC
A-5
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