Hitachi SH7750 series Hardware Manual page 805

Superh risc engine
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Figure 23.52 (1) PCMCIA Memory Bus Cycle (TED = 0, TEH = 0, No Wait)
(2) PCMCIA Memory Bus Cycle (TED = 1, TEH = 1,
One Internal Wait + One External Wait)
Rev. 4.0, 04/00, page 797 of 850

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