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Bit 0—Refresh Count Overflow Limit Select (LMTS): Specifies the count limit to be compared
with the refresh count indicated by the refresh count register (RFCR). If the RFCR register value
exceeds the value specified by LMTS, the OVF flag is set.
Bit 0: LMTS
0
1
13.2.10 Refresh Timer Counter (RTCNT)
The refresh timer counter (RTCNT) is an 8-bit readable/writable counter that is incremented by
the input clock (selected by bits CKS2–CKS0 in the RTCSR register). When the RTCNT counter
value matches the RTCOR register value, the CMF bit is set in the RTCSR register and the
RTCNT counter is cleared.
RTCNT is initialized to H'0000 by a power-on reset, but continues to count when a manual reset is
performed. In standby mode, RTCNT is not initialized, and retains its contents.
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
13.2.11 Refresh Time Constant Register (RTCOR)
The refresh time constant register (RTCOR) is a readable/writable register that specifies the upper
limit of the RTCNT counter. The RTCOR register and RTCNT counter values (lower 8 bits) are
constantly compared, and when they match the CMF bit is set in the RTCSR register and the
RTCNT counter is cleared to 0. If the refresh bit (RFSH) has been set to 1 in the memory control
register (MCR) and CAS-before-RAS has been selected as the refresh mode, a memory refresh
cycle is generated when the CMF bit is set.
Rev. 4.0, 04/00, page 306 of 850
Description
Count limit is 1024
Count limit is 512
15
14
—
—
0
0
—
—
7
6
0
0
R/W
R/W
13
12
—
—
0
0
—
—
5
4
0
0
R/W
R/W
11
10
—
—
0
0
—
—
3
2
0
0
R/W
R/W
(Initial value)
9
8
—
—
0
0
—
—
1
0
0
0
R/W
R/W
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