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T1
A25–A0
RD/
D63–D0
Area m space read
13.3.11 Bus Arbitration
The SH7750 Series is provided with a bus arbitration function that grants the bus to an external
device when it makes a bus request. Also provided is a bus arbitration function to support the
connection of two processors. The purpose of this function is to enable a multiprocessor system to
be implemented with a minimum of hardware by connecting the processors in a bus arbitration
master and slave arrangement.
There are three bus arbitration modes: master mode, partial-sharing master mode, and slave mode.
In master mode the bus is held on a constant basis, and is released to another device in response to
a bus request. In slave mode the bus is not held on a constant basis; a bus request is issued each
time an external bus cycle occurs, and the bus is released again at the end of the access. In partial-
sharing master mode, only area 2 is shared with external devices; slave mode is in effect for area
2, while for other spaces, bus arbitration is not performed and the bus is held constantly. The area
in the master mode chip to which area 2 in the partial-sharing master mode chip is allocated is
determined by an external circuit.
T2
Twait
Area m inter-access wait specification
Figure 13.72 Waits between Access Cycles
T1
T2
Twait
Area n space read
Area n inter-access wait specification
T1
T2
Area n space write
Rev. 4.0, 04/00, page 411 of 850
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