Pair Single-Precision Data Transfer - Hitachi SH7750 series Hardware Manual

Superh risc engine
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the FPU state. With the FRCHG instruction, an FPSCR.FR bit modification can be performed in
one cycle.
6.6.2

Pair Single-Precision Data Transfer

In addition to the powerful new geometric operation instructions, the SH7750 Series also supports
high-speed data transfer instructions.
When FPSCR.SZ = 1, the SH7750 Series can perform data transfer by means of pair single-
precision data transfer instructions.
• FMOV DRm/XDm, DRn/XDRn (m, n: 0, 2, 4, 6, 8, 10, 12, 14)
• FMOV DRm/XDm, @Rn (m: 0, 2, 4, 6, 8, 10, 12, 14; n: 0 to 15)
These instructions enable two single-precision (2 × 32-bit) data items to be transferred; that is, the
transfer performance of these instructions is doubled.
• FSCHG
This instruction changes the value of the SZ bit in FPSCR, enabling fast switching between
use and non-use of pair single-precision data transfer.
Programming Note
When FPSCR.SZ = 1 and big-endian mode is used, FMOV can be used for a double-precision
floating-point load or store. In little-endian mode, a double-precision floating-point load or store
requires execution of two 32-bit data size operations with FPSCR.SZ = 0.
Rev. 4.0, 04/00, page 128 of 850

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