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Initial settings
(SAR, DAR, DMATCR,
CHCR, DMAOR)
DE, DME = 1?
Yes
Illegal address check
(reflected in AE bit)
NMIF, AE, TE = 0?
Yes
Transfer
request issued?
*1
Yes
Transfer (1 transfer unit)
DMATCR - 1 → DMATCR
Update SAR, DAR
DMATCR = 0?
Yes
DMTE interrupt request
(when IE = 1)
NMIF or
AE = 1 or DE = 0 or
DME = 0?
Yes
End of transfer
Notes: 1. In auto-request mode, transfer begins when the NMIF, AE, and TE bits are all 0, and the DE
and DME bits are set to 1.
2.
3.
4. An illegal address is detected by comparing bits TS2–TS0 in CHCRn with SARn and DARn.
Rev. 4.0, 04/00, page 440 of 850
No
*4
No
No
No
No
Normal end
level detection (external request) in burst mode, or cycle steal mode.
edge detection (external request) in burst mode, or auto-request mode in burst mode.
Figure 14.2 DMAC Transfer Flowchart
*3
NMIF or
No
AE = 1 or DE = 0 or
DME = 0?
Yes
Transfer suspended
*2
Bus mode,
transfer request mode,
detection
method
No
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