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9.1.2
Register Configuration
Table 9.2 shows the registers used for power-down mode control.
Table 9.2
Power-Down Mode Registers
Name
Standby control register
Standby control register 2 STBCR2
9.1.3
Pin Configuration
Table 9.3 shows the pins used for power-down mode control.
Table 9.3
Power-Down Mode Pins
Pin Name
Processor status 1
Processor status 0
Note: H: High level
L: Low level
9.2
Register Descriptions
9.2.1
Standby Control Register (STBCR)
The standby control register (STBCR) is an 8-bit readable/writable register that specifies the
power-down mode status. It is initialized to H'00 by a power-on reset via the 5(6(7 pin or due to
watchdog timer overflow.
Bit:
Initial value:
R/W:
Abbreviation
STBCR
Abbreviation
STATUS1
STATUS0
7
6
STBY
PHZ
0
0
R/W
R/W
Initial
R/W
Value
P4 Address
R/W
H'00
H'FFC00004 H'1FC00004
R/W
H'00
H'FFC00010 H'1FC00010
I/O
Function
Output
Indicate the processor's operating status.
HH: Reset
HL: Sleep mode
LH: Standby mode
LL: Normal operation
5
4
PPU
MSTP4
MSTP3
0
0
R/W
R/W
Area 7
Address
3
2
MSTP2
MSTP1
0
0
R/W
R/W
Rev. 4.0, 04/00, page 179 of 850
Access
Size
8
8
1
0
MSTP0
0
0
R/W
R/W
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