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Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using a
multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to
the transmit data.
The MPBT bit setting is invalid in synchronous mode, when a multiprocessor format is not used,
and when the operation is not transmission.
Unlike transmit data, the MPBT bit is not double-buffered, so it is necessary to check whether
transmission has been completed before changing its value.
Bit 0: MPBT
0
1
15.2.8
Serial Port Register (SCSPTR1)
Bit:
7
EIO
Initial value:
0
R/W:
R/W
SCSPTR1 is an 8-bit readable/writable register that controls input/output and data for the port pins
multiplexed with the serial communication interface (SCI) pins. Input data can be read from the
RxD pin, output data written to the TxD pin, and breaks in serial transmission/reception
controlled, by means of bits 1 and 0. SCK pin data reading and output data writing can be
performed by means of bits 3 and 2. Bit 7 controls enabling and disabling of the RXI interrupt.
SCSPTR1 can be read or written to by the CPU at all times. All SCSPTR1 bits except bits 2 and 0
are initialized to 0 by a power-on reset or manual reset; the value of bits 2 and 0 is undefined.
SCSPTR1 is not initialized in the module standby state or standby mode.
Bit 7—Error Interrupt Only (EIO): When the EIO bit is 1, an RXI interrupt request is not sent
to the CPU even if the RIE bit is set to 1. When the DMAC is used, this setting means that only
ERI interrupts are handled by the CPU. The DMAC transfers read data to memory or another
peripheral module. This bit specifies enabling or disabling of the RXI interrupt.
Bit 7: EIO
0
1
Description
Data with a 0 multiprocessor bit is transmitted
Data with a 1 multiprocessor bit is transmitted
6
5
—
—
0
0
—
—
Description
The RIE bit enables/disables RXI and ERI interrupts
When the RIE bit is 1, RXI and ERI interrupts are sent to INTC(Initial value)
When the RIE bit is 1, only ERI interrupts are sent to INTC
4
3
—
SPB1IO SPB1DT SPB0IO SPB0DT
0
0
—
R/W
Rev. 4.0, 04/00, page 519 of 850
(Initial value)
2
1
—
0
R/W
R/W
0
—
R/W
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