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21.2.2
Data Register (SDDR)
The data register (SDDR) is a 32-bit register, comprising the two 16-bit registers SDDRH and
SDDRL, that can be read and written to by the CPU. The value in this register is not initialized by
a 7567 or CPU reset.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Note: *: Undefined
Bits 31 to 0—DR Data: These bits store the SDDR value.
21.2.3
Bypass Register (SDBPR)
The bypass register (SDBPR) is a one-bit register that cannot be accessed by the CPU. When
bypass mode is set in SDIR, SDBPR is connected between the TDI pin and TDO pin of the
H-UDI.
Rev. 4.0, 04/00, page 708 of 850
31
30
*
*
R/W
R/W
23
22
*
*
R/W
R/W
15
14
*
*
R/W
R/W
7
6
*
*
R/W
R/W
29
28
*
*
R/W
R/W
21
20
*
*
R/W
R/W
13
12
*
*
R/W
R/W
5
4
*
*
R/W
R/W
27
26
*
*
R/W
R/W
19
18
*
*
R/W
R/W
11
10
*
*
R/W
R/W
3
2
*
*
R/W
R/W
25
24
*
*
R/W
R/W
17
16
*
*
R/W
R/W
9
8
*
*
R/W
R/W
1
0
*
*
R/W
R/W
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