Hitachi SH7750 series Hardware Manual page 778

Tpr
CKIO
t
BANK
Precharge-sel
Addr
t
t
RD/
t
t
DQMn
D63–D0
(read)
t
D63–D0
(write)
CKE
t
DACKn
(SA: IO ← memory)
Figure 23.26 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ
Commands, Burst (TPC = 1, RCD = 1, CAS Latency = 3)
Rev. 4.0, 04/00, page 770 of 850
Tpc Tr Trw
t
AD AD
Row
Row
Row
CSD
t
RWD RWD
t
t t
RASD
RASD
RASD
t
CASD2 CASD2
WDD
DACD
Tc1 Tc2 Tc3
t
AD
H/L
c0
RASD
t
CASD2
t
DQMD
Td3
Tc4/Td1 Td2
t
DQMD
t t
RDS RDH
d0 d1 d2
t t
BSD BSD
t
DACD
Td4
t
AD
t
CSD
d3
t
WDD
t
DACD