Hitachi SH7750 series Hardware Manual page 767

Note: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 23.15 SRAM Bus Cycle: Basic Bus Cycle (No Wait)
CKIO
t
A25 – A0
t
t
RD/
t
D63 – D0
(read)
t
WED1
t
WDD
D63 – D0
(write)
t
BSD
t
DACD
DACKn
(SA: IO ← memory)
t
DACDF
DACKn
(SA: IO → memory)
t
DACD
DACKn
(DA)
T1 T2
t
AD AD
t
CSD CSD
t
RWD RWD
t t
RSD RSD RSD
t
RDS
t t
WEDF WEDF
t t
WDD WDD
t
BSD
t t
DACD DACD
t
DACDF
t
DACD
Rev. 4.0, 04/00, page 759 of 850
t
RDH