Hitachi SH7750 series Hardware Manual page 402

Superh risc engine
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Tm1
Tmd1
CKIO
/
D63–D0
A
D0
RD/
DACKn
(DA)
Figure 13.54 MPX Interface Timing 3
(Single Write Cycle, AnW = 0, No Wait, Bus Width: 64 Bits)
Rev. 4.0, 04/00, page 391 of 850

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