Hitachi H8S/2646 Hardware Manual page 1038

BCRH—Bus Control Register H
Bit 7
ICIS1
Initial value 1
R/W
Read/Write
Idle Cycle Insert 1
0
1
1006
6 5
ICIS0 BRSTRM
1 0
R/W R/W
Burst ROM Enable
0 Area 0 is basic bus interface
1 Area 0 is burst ROM interface
Idle Cycle Insert 0
0 Idle cycle not inserted in case of successive external
read and external write cycles
Idle cycle inserted in case of successive external
1
read and external write cycles
Idle cycle not inserted in case of successive external
read cycles in different areas
Idle cycle inserted in case of successive external
read cycles in different areas
H'FED4
4 3
BRSTS1 BRSTS0
1 0
R/W R/W
Burst Cycle Select 0
0 Max. 4 words in burst access
1 Max. 8 words in burst access
Burst Cycle Select 1
0 Burst cycle comprises 1 state
1 Burst cycle comprises 2 states
Bus Controller
2 1
— —
0 0
R/W R/W R/W
0
—
0