Xilinx ZCU1285 User Manual page 70

After entering a clock file, the current settings and frequencies are listed to the right of the
relevant fields. To change the output divisors of an LMK04208 clock source, enter the new
divisor in the Output Divisor field and press Enter. To disable or enable an output, use the
Output PwrDwn field. A "0" enables the output and a "1" disables it.
Set CLK-103 LMX2592 PLL A, B, and C Frequency
Enter the full file name of the clock file with the desired frequency for PLL A in the field next to
the Type file name in the clockFiles/lmx2592a folder and press Enter or click the Set
LMX2592_A Frequency button (see following the figure). The same can be done for PLL B and C
in the next two fields down. Be sure to enter the exact file names from the associated folders.
After the frequency is set, the Logging pane shows no errors and prints Finished.
UG1348 (v1.0) July 16, 2019
ZCU1285 Board User Guide
Figure 34: CLK-103 Set LMK04208 Frequency
Appendix E: System Controller
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