Xilinx ZCU1285 User Manual page 40

PLL B and C
PLL B and C have two differential output SMA pairs each that are used as RF sampling clocks for
RF-DACs. Each PLL is programmable to any frequency up to 6.4 GHz with a phase noise
performance of -130 dBc/Hz at 1 MHz offset from the carrier and individually programmable
output power levels up to 6 dBm. The default boot frequency for each of these PLLs is 4.9152
GHz and a typical output power level is 4 dBm.
General Purpose Clocks
The general-purpose clocks are three pairs of phase-aligned LVDS clocks (SYS_REF_1,
SYS_REF_2, and FPGA_REF_CLK) programmable to any frequency up to 1.0 GHz. Each clock pair
can be individually enabled or disabled. The default boot state for these clocks is disabled.
Single-Ended Reference Clock
The single-ended reference clock is an LVCMOS output that can be enabled or disabled, and is
programmable to any frequency up to 250 MHz. The default boot frequency for this clock is 12.8
MHz.
Programming the Clocks
The clocks on the SuperClock-RF2 Module can be programmed using the System Controller user
interface (SCUI). See
the System Controller user interface. The clock files contain PLL register values used to program
the clocks to a pre-set frequency. To create custom clock files, contact
SuperClock-RF2 Pin Mapping
The SuperClock-RF2 Module maps to RFSoC I/O by way of two I2C signals. The following table
lists the RFSoC I/O mapping for the SuperClock-RF2 Module interface. To connect to the
SuperClock-RF2 Module using the I2C bus, see
Table 20: RFSoC PS to UART Connection
Pin Function
AM26 Control I/O
AP23 Control I/O
UG1348 (v1.0) July 16, 2019
ZCU1285 Board User Guide
Appendix E: System Controller. A set of clock files are provided along with
RFSoC (U1)
IOSTANDAR
Direction
D
Bidir LVCMOS
Bidir LVCMOS
Chapter 1: ZCU1285 Board Features and Operation
Texas
I2C Bus Management.
Schematic Net
Name
Pin
ACM_SCL/ 62
DUT_PMBUS_CLK
ACM_SDA/ 64
DUT_PMBUS_DATA
Send Feedback
Instruments.
J170 Pin
Function Direction
I2C Bidir
I2C Bidir
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