Xilinx ZCU1285 User Manual page 39

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Table 19: SuperClock-RF2 Interface Connections
Callouts
1
2
3
4
5
6
7
PLL A
PLL A has four differential output SMA pairs that are used as RF sampling clocks for RF-ADCs.
They are programmable to any frequency up to 4.0 GHz with a phase noise performance of -133
dBc/Hz at 1 MHz offset from the carrier and a typical output power level of 3 dBm at 4 GHz. The
default boot frequency for this PLL is 3.93216 GHz.
UG1348 (v1.0) July 16, 2019
ZCU1285 Board User Guide
Figure 15: SuperClock-RF2 Module Features
6 5
Reference Designators
J12, J13, J14, J15, J16, J17, J18, J19
J4, J5, J6, J7, J8, J9
J20, J21, J22, J23
J26, J27, J28, J29
J11
J10
DS1, DS2, DS3, DS5
Chapter 1: ZCU1285 Board Features and Operation
2
7
4
Feature Description
PLL A RF sampling clock SMA pairs
General-purpose clock SMA pairs
PLL B RF sampling clock SMA pairs
PLL C RF sampling clock SMA pairs
External reference clock input
Single-ended reference clock output
PLL lock indicator LEDs
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