Superclock-2 Module - Xilinx ZCU1285 User Manual

Table 17: PS-GTR Transceiver Reference Clock Inputs (cont'd)
RFSoC (U1)
AD35
AC36
AC37
AB34
AB35

SuperClock-2 Module

The SuperClock-2 Module (callout 6,
clock module interface connector (J36) and provides a programmable, low-noise and low-jitter
clock source for use with the GTY and PS-GTR transceivers. The clock module maps to the
RFSoC by way of two I2C signals, two LVDS pairs, and one global clock pair. The following table
lists the RFSoC mapping for the SuperClock-2 Module interface. To program the SuperClock-2
Module using the System Controller, see
SuperClock-2 Module using the I2C bus, see
Table 18: SuperClock-2 Interface Connections
Pin Function
L28 Clock recovery
L29 Clock recovery
H10 Clock recovery
H9 Clock recovery
AP24 Global clock
AR24 Global clock
AM26 Control I/O
AP23 Control I/O
UG1348 (v1.0) July 16, 2019
ZCU1285 Board User Guide
Net Name
PS_REFCLK1_N
PS_REFCLK2_P
PS_REFCLK2_N
PS_REFCLK3_P
PS_REFCLK3_N
Figure 2: Board Component
Appendix E: System
RFSoC (U1)
IOSTANDAR
Direction
D
Input LVDS
Input LVDS
Input LVDS
Input LVDS
Input LVDS
Input LVDS
Bidir LVCMOS
Bidir LVCMOS
Chapter 1: ZCU1285 Board Features and Operation
Bank
505
505
505
505
505
Locations) connects to the
Controller. To connect to the
I2C Bus Management.
Schematic Net
Name
Pin
CM_LVDS1_P 1
CM_LVDS1_N 3
CM_LVDS2_P 9
CM_LVDS2_N 11
CM_GCLK_P 25
CM_GCLK_N 27
CM_I2C_SCL/ 62
DUT_PMBUS_CLK
CM_I2C_SDA/ 64
DUT_PMBUS_DATA
Send Feedback
Connector
J39
J194
J156
J158
J159
J36 Pin
Function Direction
Clock recovery Output
Clock recovery Output
Clock recovery Output
Clock recovery Output
Global clock Output
Global clock Output
I2C Bidir
I2C Bidir
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