Kc705 Board Xdc Listing; Appendix C: Master Constraints File Listing - Xilinx KC705 User Manual

Master Constraints File Listing
The KC705 board Xilinx® design constraints (XDC) file template provides for designs
targeting the KC705 board. Net names in the constraints listed below correlate with net
names on the latest KC705 board schematic. Users must identify the appropriate pins and
replace the net names below with net names in the user RTL. See
Guide: Using Constraints
Users can refer to the XDC files generated by tools such as Memory Interface Generator
(MIG) for memory interfaces and Base System Builder (BSB) for more detailed I/O standards
information required for each particular interface. The FMC connectors J2 and J22 are
connected to 2.5V V
circuitry, the FMC bank I/O standards must be uniquely defined by each customer.
The constraints file listed in this appendix might not be the latest version. Always refer to the
Note:
Kintex-7 KC705 Evaluation Kit product page
pins constraints files (XDC files). Choose the Xilinx tools link. In the search box, search for KC705
Master XDC File.

KC705 Board XDC Listing

#CLOCKS
#SYSCLK
set_property PACKAGE_PIN AD11 [get_ports SYSCLK_N]
set_property IOSTANDARD LVDS [get_ports SYSCLK_N]
set_property PACKAGE_PIN AD12 [get_ports SYSCLK_P]
set_property IOSTANDARD LVDS [get_ports SYSCLK_P]
#USERCLK
set_property PACKAGE_PIN K29 [get_ports USER_CLOCK_N]
set_property IOSTANDARD LVDS_25 [get_ports USER_CLOCK_N]
set_property PACKAGE_PIN K28 [get_ports USER_CLOCK_P]
set_property IOSTANDARD LVDS_25 [get_ports USER_CLOCK_P]
#USER SMA CLOCK
set_property PACKAGE_PIN K25 [get_ports USER_SMA_CLOCK_N]
set_property IOSTANDARD LVDS_25 [get_ports USER_SMA_CLOCK_N]
set_property PACKAGE_PIN L25 [get_ports USER_SMA_CLOCK_P]
set_property IOSTANDARD LVDS_25 [get_ports USER_SMA_CLOCK_P]
#SI5326
set_property PACKAGE_PIN L7 [get_ports SI5326_OUT_C_N]
set_property PACKAGE_PIN L8 [get_ports SI5326_OUT_C_P]
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
(UG903) [Ref 26] for more information.
banks. Because each FMC card implements customer-specific
cco
Doc & Designs tab for the latest versions of the FPGA
www.xilinx.com
Appendix C
Vivado Design Suite User
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