Appendix C: Master Ucf Listing; Overview; Zc702 Board Ucf Listing - Xilinx ZC702 User Manual

Master UCF Listing

Overview

The ZC702 master user constraints file (UCF) template provides for designs targeting the
ZC702 board. Net names in the constraints listed below correlate with net names on the
latest ZC702 board schematic. Users must identify the appropriate pins and replace the net
names below with net names in the user RTL.
Users can refer to the UCF files generated by tools such as Memory Interface Generator
(MIG) for memory interfaces and Base System Builder (BSB) for more detailed I/O standards
information required for each particular interface. The FMC connectors J3 and J4 are
connected to 2.5V V
circuitry, the FMC bank I/O standards must be uniquely defined by each customer.
Note: The UCF file listed in this appendix might not be the latest version. Always refer to the ZC702
Evaluation Kit product page (www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm) for the
latest FPGA pins constraints file.

ZC702 Board UCF Listing

#NET FPGA_DONE
#NET XADC_DXP
#NET XADC_AGND
#NET XADC_VCC
#NET XADC_VREFP
#NET XADC_VN_R
#NET FPGA_VBATT
#NET FPGA_TCK_BUF
#NET XADC_DXN
#NET XADC_AGND
#NET XADC_VP_R
#NET GND
#NET VCC2V5
#NET VCC2V5
#NET FPGA_INIT_B
#NET FPGA_TDI_BUF
#NET JTAG_TDO_BUF
#NET VCC2V5
#NET 3N579
#NET FPGA_PROG_B
#NET FPGA_TMS_BUF
NET PL_PJTAG_TDO_R
NET PL_PJTAG_TCK
ZC702 Board User Guide
UG850 (v1.2) April 4, 2013
banks. Because each user's FMC card implements customer-specific
ADJ
LOC = T12 ; # Bank 0 - DONE_0
LOC = N11 ; # Bank 0 - DXP_0
LOC = K12 ; # Bank 0 - GNDADC_0
LOC = K11 ; # Bank 0 - VCCADC_0
LOC = M11 ; # Bank 0 - VREFP_0
LOC = M12 ; # Bank 0 - VN_0
LOC = G9 ; # Bank 0 - VCCBATT_0
LOC = G11 ; # Bank 0 - TCK_0
LOC = N12 ; # Bank 0 - DXN_0
LOC = L12 ; # Bank 0 - VREFN_0
LOC = L11 ; # Bank 0 - VP_0
LOC = G10 ; # Bank 0 - RSVDGND
LOC = T10 ; # Bank 0 - RSVDVCC
LOC = T8 ; # Bank 0 - RSVDVCC
LOC = T14 ; # Bank 0 - INIT_B_0
LOC = H13 ; # Bank 0 - TDI_0
LOC = G14 ; # Bank 0 - TDO_0
LOC = T7 ; # Bank 0 - RSVDVCC
LOC = T13 ; # Bank 0 - CFGBVS_0
LOC = T11 ; # Bank 0 - PROGRAM_B_0
LOC = G12 ; # Bank 0 - TMS_0
LOC = R7 | IOSTANDARD=LVCMOS25; # Bank 13
LOC = V10 | IOSTANDARD=LVCMOS25; # Bank 13
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Appendix C
VCCO - VADJ - IO_0_13
VCCO - VADJ - IO_L1P_T0_13
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