Appendix C: Master Ucf Listing; Vc709 Board Ucf Listing - Xilinx VC709 User Manual

Master UCF Listing
The VC709 board master user constraints file (UCF) template provides for designs
targeting the VC709 board. Net names in the constraints listed in this appendix correlate
with net names on the latest VC709 board schematic. Users must identify the appropriate
pins and replace the net names listed here with net names in the user RTL. See the
Constraints Guide for version 13.4 (UG625) for more information.
Users can refer to the UCF files generated by tools such as Memory Interface Generator
(MIG) for memory interfaces and Base System Builder (BSB) for more detailed I/O
standards information required for each particular interface. The FMC connector J35 is
connected to 1.8V V
customer-specific circuitry, the FMC bank I/O standards must be uniquely defined by each
customer.
Note:
Virtex-7 VC709 Evaluation Kit Product Page (www.xilinx.com/vc709) listed in
Resources

VC709 Board UCF Listing

VC709 Evaluation Board
UG887 (v1.0) February 4, 2013
banks. Because each user's FMC card implements
CCO
The constraints file listed in this appendix might not be the latest version. Always refer to the
for the latest FPGA pins constraints file.
#############################################
##
## VC709 Evaluation Board
## Revision A
## UCF Pin Listing
## Initial Release: June 27, 2012
##
## Updated Release: July 10, 2012
## 1. Delete SD card interface
## 2. Delete VADJ to J35 FMC1 connector
## All FMC I/O needs to be 1.8V
##
## Target FPGA: XC7VX690T-2FFG1761
##
#############################################
#############################################
##
## FPGA clock inputs
## Bank 14 VCCO = 1.8V
##
## 1. USER_CLOCK SI570
## Startup frequency = 156.25MHz
## I2C address @ 0x5D
##
## 2. USER_SMA_CLOCK
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Appendix C
Appendix F, Additional
69