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Master XDC Listing
The VC709 board master Xilinx design constraints (XDC) file template provides for
designs targeting the VC709 board. Net names in the constraints listed in this appendix
correlate with net names on the latest VC709 board schematic. Users must identify the
appropriate pins and replace the net names listed here with net names in the user RTL. See
the Vivado Design Suite User Guide Using Constraints (UG903)
Users can refer to the XDC files generated by tools such as Memory Interface Generator
(MIG) for memory interfaces and Base System Builder (BSB) for more detailed I/O
standards information required for each particular interface. The FMC connector J35 is
connected to 1.8V V
customer-specific circuitry, the FMC bank I/O standards must be uniquely defined by each
customer.
Note:
Virtex-7 FPGA VC709 Connectivity Kit Documentation website
file.
VC709 Board XDC Listing
VC709 Evaluation Board
UG887 (v1.2.1) March 11, 2014
banks. Because each user's FMC card implements
CCO
The constraints file listed in this appendix might not be the latest version. Always refer to the
set_property PACKAGE_PIN AR35 [get_ports GPIO_LED_4_LS]
set_property IOSTANDARD LVCMOS18 [get_ports GPIO_LED_4_LS]
set_property PACKAGE_PIN AU34 [get_ports SI5324_INT_ALM_LS]
set_property IOSTANDARD LVCMOS18 [get_ports SI5324_INT_ALM_LS]
set_property PACKAGE_PIN AT36 [get_ports SI5324_RST_LS]
set_property IOSTANDARD LVCMOS18 [get_ports SI5324_RST_LS]
set_property PACKAGE_PIN AU36 [get_ports USB_UART_RX]
set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_RX]
set_property PACKAGE_PIN AT32 [get_ports USB_UART_RTS]
set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_RTS]
set_property PACKAGE_PIN AU33 [get_ports USB_UART_TX]
set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_TX]
set_property PACKAGE_PIN AR34 [get_ports USB_UART_CTS]
set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_CTS]
set_property PACKAGE_PIN AT35 [get_ports IIC_SCL_MAIN_LS]
set_property IOSTANDARD LVCMOS18 [get_ports IIC_SCL_MAIN_LS]
set_property PACKAGE_PIN AU32 [get_ports IIC_SDA_MAIN_LS]
set_property IOSTANDARD LVCMOS18 [get_ports IIC_SDA_MAIN_LS]
set_property PACKAGE_PIN AV33 [get_ports PCIE_WAKE_B_LS]
set_property IOSTANDARD LVCMOS18 [get_ports PCIE_WAKE_B_LS]
set_property PACKAGE_PIN AW32 [get_ports REC_CLOCK_C_P]
set_property IOSTANDARD LVDS [get_ports REC_CLOCK_C_P]
set_property PACKAGE_PIN AW33 [get_ports REC_CLOCK_C_N]
set_property IOSTANDARD LVDS [get_ports REC_CLOCK_C_N]
set_property PACKAGE_PIN AV35 [get_ports PCIE_PERST_LS]
set_property IOSTANDARD LVCMOS18 [get_ports PCIE_PERST_LS]
www.xilinx.com
Appendix C
[Ref 9]
for more information.
for the latest FPGA pins constraints
71
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