Enable Bit (Cen)—Ccsr Bit 0; Processing Enable Bit (Pren)—Ccsr Bit 1; Operating Mode Bits (Opm[1:0])—Ccsr Bits 5–4; Figure 14-8 Ccop Control Status Register (Ccsr) - Motorola DSP56305 User Manual

reset state (CEN = 0). Other control bits in CCSR can be changed when CCOP is in the
CCOP individual reset state, or when the processing is idle (PREN = 0).
11 10
FOSH HOZD LRC
23 22
PCDN CIDN OFNE INFE INBE
Reserved bit, Read as zero, should be written with zero for future compatibility

Figure 14-8 CCOP Control Status Register (CCSR)

14.4.4.1 Enable bit (CEN)—CCSR Bit 0
The CCSR Enable bit (CEN), when set, enables the operation of the CCOP. When CEN is
cleared, the operation is disabled and the CCOP is in the CCOP individual reset state.
While in the CCOP individual reset state, internal state machine logic and status bits are
reset to the same state produced by hardware or software reset, while control bits are not
affected.
14.4.4.2 Processing Enable bit (PREN)—CCSR Bit 1
The Processing Enable bit (PREN), when set, enables the CCOP to start processing
according to the specified configuration, counter settings and control bits. When CEN is
set and PREN is cleared, CCOP is in the Idle state. While in the Idle state, all CCOP
processing is frozen and data in registers and the FIFO is preserved, thus allowing the
programmer to read, write or modify counters, shifters, configuration and control
registers as well as accessing the FIFO. The counters, CFSR configuration registers and
control registers must be assigned prior to setting PREN. Following assertion, the PREN
bit is cleared automatically by the internal logic after completion of some sort of
processing depending on the selected operation mode. While not in the Step-by-step
mode, PREN is cleared at the end of the shift processing, i.e. after the input, run and
output phases have been completed. While in the Step-by-step mode (OPM[1:0] = 01)
PREN is cleared (and thus returns to the Idle state) after executing one single shift. PREN
can also be explicitly cleared by software forcing cessation of operation.
14.4.4.3 Operating Mode bits (OPM[1:0])—CCSR Bits 5–4
The Operating Mode bits (OPM[1:0]) are used to determine the CFSR's mode of
operation. The operating modes supported in CCOP are shown in Table . OPM[1:0]
should be changed only when CCOP is in CCOP individual reset.
MOTOROLA
9 8 7 6
21 20 19 18
DSP56305 User's Manual
CYCLIC CODE CO-PROCESSOR
CCOP Programming Model
5 4 3
OPM1 OPM0
17 16 15
PDIE CDIE DOIE
2 1 0
PREN CEN
14 13 12
DIIE
AA1307
14-15