Pci Master Wait State (Mws) Bit 0; Pci Master Transmit Data Request (Mtrq) Bit 1 - Motorola DSP56305 User Manual

6.5.6.1

PCI Master Wait State (MWS) Bit 0

The MWS bit indicates that the HI32, as master in a PCI transaction, will insert wait
states (if enabled, i.e. the MWSD bit in the DPCR is cleared) to extend the current data
phase (or the first data phase if the transaction has not been initiated yet) by deasserted
HIRDY as it cannot guarantee completion of the next data phase.
MWS is set:
• In a PCI write transaction, if there is only one word in the HI32-to-host data path.
• In a PCI read transaction, if there is only one empty location in the host-to-DSP
data path.
This has many applications. For example, the DSP56300 core can set MTT, when MWS is
set, to terminate a transaction after the transfer of a specific number of words. After MTT
is set the HI32 will complete the data phase and terminate the transaction.
Hardware, software and personal software resets clear MWS.
6.5.6.2

PCI Master Transmit Data Request (MTRQ) Bit 1

The MTRQ bit indicates that the DSP master transmit data FIFO (DTXM) is not full and
can be written by the DSP56300 core. MTRQ is cleared if the DTXM is filled by DSP56300
core writes. MTRQ is set when data is output from the DTXM-HRXM FIFO to the host
bus.
If MTRQ is set
• if MTIE is set, a master transmit data interrupt request is generated
• if enabled by an DSP56300 core DMA channel, a master transmit data DMA
request will be generated.
Hardware, software and personal software resets set MTRQ. In the personal software
reset state MTRQ = 0.
MOTOROLA DSP56305 User's Manual
HOST INTERFACE (HI32)
DSP SIDE Programming Model
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