Motorola DSP56156 Manuals

Manuals and User Guides for Motorola DSP56156. We have 1 Motorola DSP56156 manual available for free PDF download: Manual

Motorola DSP56156 Manual

Motorola DSP56156 Manual (330 pages)

Brand: Motorola | Category: Signal Processors | Size: 1.26 MB

Table of Contents

Table of Contents

1
- Dsp56156 Overview
  22
Section 1

23
- Introduction
  24
- Dsp56100 Core Block Diagram Description
  27
- Address Buses
  29
- Data Buses
  29
- Data ALU
  30
- Address Generation Unit (AGU)
  31
- Program Control Unit (PCU)
  32
- Exception Priorities Within an IPL
  38
- Interrupt Priority Levels (IPL)
  38
- Interrupt Priority Structure
  38
- Memory Organization
  38
- External Bus, I/O, and On-Chip Peripherals
  39
- General Purpose I/O (Port B, Port C)
  40
- Memory Expansion Port (Port A)
  40
- SSI0 and SSI1
  40
- Host Interface (HI)
  41
- Timer
  41
- Data ALU
  42
- Once
  42
- Programming Model
  42
- Address Generation Unit
  44
- Address Register File (R0-R3)
  44
- Data ALU Accumulator Registers (A2, A1, A0, B2, B1, B0)
  44
- Data ALU Input Registers (X1, X0, Y1, Y0)
  44
- Modifier Register File (M0-M3)
  45
- Offset Register File (N0-N3)
  45
- Program Control Unit
  45
- Program Counter (PC)
  45
- Status Register (SR)
  45
- Loop Counter (LC)
  46
- Loop Address Register (LA)
  47
- Stack Pointer (SP)
  47
- System Stack (SS)
  47
- Operating Mode Register (OMR)
  48
- Instruction Groups
  50
- Instruction Set Summary
  50
- Arithmetic Instructions
  51
- Logical Instructions
  52
- Bit Field Manipulation Instructions
  53
- Loop Instructions
  53
- Move Instructions
  53
- Instruction Formats
  54
- Program Control Instructions
  54
- Addressing Modes
  55
- Address Arithmetic
  57
- Linear Modifier
  57
- Reverse Carry Modifier
  57
- Dsp56156 Pin Descriptions
  58
Section 2

59
- Address and Data Bus (32 Pins)
  60
- Bus Control (9 Pins)
  60
- Introduction
  60
- Interrupt and Mode Control (3 Pins)
  66
- Power, Ground, and Clock (28 Pins)
  67
- Host Interface (15 Pins)
  68
- 16-Bit Timer (2 Pins)
  69
- Synchronous Serial Interfaces (Ssi0 and Ssi1) (10 Pins)
  69
- On-Chip Emulation (4 Pins)
  70
- On-Chip Codec (7 Pins)
  71
- Operating Modes and Memory Spaces
  72
- DSP56156 RAM Part Memory Introduction
  74
- Ram Memory Description
  74
- Bootstrap Memory
  75
- Data Memory
  75
- Program Memory
  75
- Bootstrap Mode (Mode 0)
  76
- Chip Operating Modes
  76
- Bootstrap Mode
  77
- Bootstrap Mode (Mode 1)
  77
- Bootstrap ROM
  77
- Development Mode (Mode 3)
  77
- Normal Expanded Mode (Mode 2)
  77
- Bootstrap Control Logic
  78
- Bootstrap Program
  78
- DSP56156 ROM Part Memory Introduction
  80
- Rom Memory Description
  80
- Chip Operating Modes
  81
- Data Memory
  81
- Program Memory
  81
- Single-Chip Mode (Mode 0)
  81
- Development Mode (Mode 3)
  82
- Mode 1
  82
- Normal Expanded Mode (Mode 2)
  82
- I/O Port Set-Up and Programming
  86
- Introduction
  86
- Bus Control Register (BCR)
  87
- Port Registers
  87
- Port B and Port C Registers
  89
- Host Interface
  92
- Host Interface (15 Pins)
  92
Section 3

93
Section 4

117
- General Description
  118
- Introduction
  118
- Analog I/O Definition
  119
- Interface Definition
  120
- Interface with the Dsp56156 Core Processor
  120
- Codec Receive Register (CRX)
  121
- Codec Transmit Register (CTX)
  121
- On-Chip Codec Programming Model
  121
- COCR Audio Level Control Bits (VC3-VC0) Bits 0-3
  122
- Codec Control Register (COCR)
  122
- COCR Microphone Gain Select Bits (MGS1-0) Bits 11,12
  123
- COCR Mute Bit (MUT) Bit 10
  123
- COCR Codec Enable Bit (COE) Bit 14
  124
- COCR Codec Interrupt Enable Bit (COIE) Bit 15
  124
- COCR Input Select Bit (INS) Bit 13
  124
- COCR Reserved Bits (Bits 4-7)
  124
- Codec Status Register (COSR)
  124
- COSR Codec Transmit under Run Error Flag Bit (CTUE) Bit 0
  124
- COSR Codec Receive Data Full Bit (CRDF) Bit 3
  125
- COSR Codec Receive Overrun Error Flag Bit (CROE) Bit 1
  125
- COSR Codec Transmit Data Empty Bit (CTDE) Bit 2
  125
- COSR Reserved Bits (Bits 4-15)
  125
- A/D Section Frequency Response and DC Gain
  127
- On-Chip Codec Frequency Response and Gain Analysis
  127
- D/A Section Frequency Response and DC Gain
  132
- D/A Second Order Digital Comb Filter
  134
- D/A Analog Comb Decimating Filter
  136
- D/A Analog Low Pass Filter
  139
- D/A Section Overall Frequency Response
  141
- Application Examples
  145
- Example 1
  145
- A/D Decimation DSP Filter
  147
- D/A Interpolation Filter
  150
- Example 3
  153
- A/D Decimation DSP Filter
  155
- D/A Interpolation Filter
  158
- Example 5 - Real-Time I/O Example with On-Chip Codec and PLL
  177
- Dsp Program Flowchart
  180
- 16-Bit Timer and Event Counter
  184
Section 5

185
- Introduction
  186
- Timer Architecture
  186
- Timer Count Register (Tctr)
  186
- Timer Preload Register (Tpr)
  187
- Timer Compare Register (Tcpr)
  188
- TCR Decrement Ratio (DC7-DC0) Bit 0-7
  189
- TCR Event Select (ES) Bit 8
  189
- TCR Overflow Interrupt Enable (OIE) Bit 9
  189
- Timer Control Register (Tcr)
  189
- TCR Compare Interrupt Enable (CIE) Bit 10
  190
- TCR Inverter Bit (INV) Bit 14
  190
- TCR Timer Output Enable (TO2-TO0) Bit 11-13
  190
- Functional Description of the Timer
  191
- TCR Timer Enable (TE) Bit 15
  191
- Timer Resolution
  191
- Functional Description of the Timer
  192
- SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1)
  198
Section 6

199
- Introduction
  200
- Ssi Operating Modes
  200
- Ssi Clock and Frame Sync Generation
  201
- Ssix DATA and CONTROL PINS
  201
- Ssix DATA and CONTROL PINS
  202
- Serial Clock - SCK
  204
- Serial Control - Sc1X
  204
- Serial Receive Data Pin - Srdx
  204
- Serial Transmit Data Pin - Stdx
  204
- Serial Control - Sc0X
  205
- Ssi Reset and Initialization Procedure
  205
- Ssix INTERFACE PROGRAMMING MODEL
  206
- Ssi Transmit Shift Register
  207
- Ssi Control Register a (Cra)
  209
- Ssi Receive Data Register (Rx)
  209
- Ssi Receive Shift Register
  209
- Ssi Transmit Data Register (Tx)
  209
- CRA Frame Rate Divider Control (DC0
  210
- CRA Prescale Modulus Select (PM0
  210
- Ssi Control Register a (Cra)
  210
- CRA Word Length Control (WL0,WL1) Bits 13, 14
  211
- CRA Prescaler Range (PSR) Bit 15
  212
- Ssi Control Register B (Crb)
  212
- CRB Serial Output Flag 0 and 1 (OF0, OF1) Bit 0, 1
  213
- Transmit and Receive Frame Sync Directions - (FSD0, FSD1) Bit 2,4
  213
- CRB A/Mu Law Selection Bit (A/MU) Bit 3
  214
- CRB Clock Polarity Bit (SCKP) Bit 6
  214
- CRB Clock Source Direction (SCKD) Bit 5
  214
- CRB Frame Sync Invert (FSI) Bit 9
  214
- CRB Frame Sync Length (FSL) Bit 8
  214
- CRB MSB Position Bit (SHFD) Bit 7
  214
- Transmit and Receive Frame Sync Directions - (FSD1) Bit 4
  214
- CRB SSI Mode Select (MOD) Bit 11
  215
- CRB Sync/Async (SYN) Bit 10
  215
- Ssi Status Register (Ssisr)
  216
- Time Slot Register - Tsr
  219
- TRANSMIT SLOT MASK REGISTERS - Tsmax and Tsmbx
  219
- RECEIVE SLOT MASK REGISTERS - Rsmax and Rsmbx
  220
- Transmit Slot Mask Shift Register - Tsms
  220
- Receive Slot Mask Shift Register - Rsms
  221
- Ssi Operating Modes
  221
Section 7

227
- Introduction
  228
- Ssi Operating Modes
  228
- Ssi Clock and Frame Sync Generation
  229
- Ssix DATA and CONTROL PINS
  229
- Ssi Reset and Initialization Procedure
  233
- Ssix INTERFACE PROGRAMMING MODEL
  234
- Ssi Transmit Shift Register
  235
- Ssi Control Register a (Cra)
  237
- Ssi Receive Data Register (Rx)
  237
- Ssi Receive Shift Register
  237
- Ssi Transmit Data Register (Tx)
  237
- Ssi Control Register B (Crb)
  240
- Ssi Status Register (Ssisr)
  244
- Time Slot Register - Tsr
  247
- TRANSMIT SLOT MASK REGISTERS - Tsmax and Tsmbx
  247
- RECEIVE SLOT MASK REGISTERS - Rsmax and Rsmbx
  248
- Transmit Slot Mask Shift Register - Tsms
  248
- Receive Slot Mask Shift Register - Rsms
  249
- Ssi Operating Modes
  249

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