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Motorola DSP56012 User Manual

24-bit digital signal processor
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24-Bit Digital Signal Processor
Motorola, Incorporated
Semiconductor Products Sector
DSP Division
6501 William Cannon Drive West
Austin, TX 78735-8598
DSP56012
User's Manual
DSP56012UM/D
Rev. 0
Published 11/98

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  • Page 1 DSP56012UM/D Rev. 0 Published 11/98 DSP56012 24-Bit Digital Signal Processor User’s Manual Motorola, Incorporated Semiconductor Products Sector DSP Division 6501 William Cannon Drive West Austin, TX 78735-8598...
  • Page 2 All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components...

  • Page 3: Table Of Contents

    PHASE LOCK LOOP (PLL)......2-7 INTERRUPT AND MODE CONTROL ....2-8 Motorola...
  • Page 4 Programming Model—DSP Viewpoint ....4-13 4.4.4.1 HI Control Register (HCR) ..... 4-14 4.4.4.1.1 HCR HI Receive Interrupt Enable (HRIE)—Bit 0 . 4-15 Motorola...
  • Page 5 Interrupt Status Register (ISR)....4-30 4.4.5.6.1 ISR Receive Data Register Full (RXDF)—Bit 0. . . 4-30 4.4.5.6.2 ISR Transmit Data Register Empty (TXDE)—Bit 1 4-31 4.4.5.6.3 ISR Transmitter Ready (TRDY)—Bit 2 ..4-31 Motorola...
  • Page 6 HI Port Usage Considerations—Host Side ..4-65 4.4.8.4.1 Unsynchronized Reading of Receive Byte Registers4-65 4.4.8.4.2 Overwriting Transmit Byte Registers... 4-66 4.4.8.4.3 Synchronization of Status Bits from DSP to Host . 4-66 Motorola...
  • Page 7 HCSR Host Transmit Data Empty (HTDE)—Bit 15 . . 5-17 5.4.6.14 Host Receive FIFO Not Empty (HRNE)—Bit 17 ..5-18 5.4.6.15 Host Receive FIFO Full (HRFF)—Bit 19 ..5-18 Motorola...
  • Page 8 RCS Receiver Left Right Selection (RLRS)—Bit 7 . . 6-12 6.3.2.8 RCS Receiver Clock Polarity (RCKP)—Bit 8 ..6-13 6.3.2.9 RCS Receiver Relative Timing (RREL)—Bit 9..6-13 viii Motorola...
  • Page 9 OVERVIEW........8-3 DAX SIGNALS ........8-4 Motorola...
  • Page 10 BOOTSTRAPPING THE DSP......A-3 BOOTSTRAP PROGRAM LISTING ....A-4 Motorola...
  • Page 11 INSTRUCTION SET SUMMARY ..... B-3 PROGRAMMING SHEETS......B-3 Motorola...
  • Page 12 Motorola...

  • Page 13: List Of Figures

    HI Register Map ........4-24 Figure 4-12 HSR and HCR Operation ......4-26 Motorola xiii...
  • Page 14 Main Program: Transmit 24-bit Data to Host ....4-59 Figure 4-35 HI Hardware–DMA Mode ......4-60 Motorola...
  • Page 15 Receiver Relative Timing (RREL) Programming ... .6-14 Figure 6-9 Receiver Data Word Truncation (RDWT) Programming ..6-14 Figure 6-10 Transmitter Data Shift Direction (TDIR) Programming ..6-19 Motorola...
  • Page 16 Clock Multiplexer Diagram ......8-13 Figure B-1 On-chip Peripheral Memory Map ......B-4 Motorola...
  • Page 17 Table 3-4 Interrupt Priorities ........3-16 Motorola xvii...
  • Page 18 Preamble Bit Patterns ....... .8-12 Table B-1 Interrupt Starting Addresses and Sources ....B-5 xviii Motorola...
  • Page 19 Interrupt Priorities Within an IPL ......B-6 Table B-3 Instruction Set Summary (Sheet 1 of 7)....B-8 Motorola...
  • Page 20 Motorola...
  • Page 21 SECTION 1 OVERVIEW MOTOROLA DSP56012 User’s Manual...
  • Page 22 Input/Output ........1-16 DSP56012 User’s Manual MOTOROLA...

  • Page 23: Introduction

    Processing Unit (CPU), programming models, and the instruction set. The data sheet provides electrical specifications, timing, pinouts, and packaging descriptions. These documents, as well as Motorola’s DSP development tools, can be obtained through a local Motorola Semiconductor Sales Office or authorized distributor.

  • Page 24: Manual Organization

    • Appendix B—Programming Reference provides a quick reference for the instructions and registers used by the DSP56012. These sheets are provided with the expectation that they be photocopied and used by programmers when programming the registers. DSP56012 User’s Manual MOTOROLA...

  • Page 25: Manual Conventions

    (see Table 1-1 ). For example, the RESET pin is active when pulled to ground. Therefore, references to the RESET pin will always have an overbar. Such pins and signals are also said to be “active low” or “low true.” MOTOROLA DSP56012 User’s Manual...

  • Page 26: Dsp56012 Features

    – 56-bit addition/subtraction in 1 instruction cycle – Fractional and integer arithmetic with support for multi-precision arithmetic – Hardware support for block-floating point Fast Fourier Transforms (FFT) – Hardware nested DO loops – Zero-overhead fast interrupts (2 instruction cycles) DSP56012 User’s Manual MOTOROLA...

  • Page 27: Table 1-2 Dsp56012 Internal Memory Configurations

    – SAI includes: • Two receivers and three transmitters • Master or slave capability • I S, Sony, and Matshushita audio protocol implementations These ROMs may be factory programmed with data/program provided by the application developer. MOTOROLA DSP56012 User’s Manual...

  • Page 28: Dsp56012 Architectural Overview

    The DSP56000-family architecture, upon which the DSP56012 is built, was designed to maximize throughput in data-intensive digital signal processing applications. The result is a dual-natured, expandable architecture with sophisticated on-chip peripherals and versatile GPIO. DSP56012 User’s Manual MOTOROLA...

  • Page 29: Figure 1-1 Dsp56012 Block Diagram

    16-bit and 32-bit architectures—16-bit DSP architectures have insufficient precision for CD-quality sound, and while 32-bit DSP architectures possess the necessary precision, with extra silicon and cost overhead they are not suitable for high-volume, cost-driven audio applications MOTOROLA DSP56012 User’s Manual...

  • Page 30: Peripheral Modules

    DSP56012 to a host processor or to another serial peripheral device. Two serial protocols are available: the Motorola Serial Peripheral Interface (SPI) bus and the Philips Inter Integrated-circuit Control (I C) bus. The SHI will operate with 8-, 16-, and 24-bit words and the receiver contains an optimal 10-word First-In, First-Out (FIFO) register to reduce the receive interrupt rate.

  • Page 31: Data Arithmetic And Logic Unit (Data Alu)

    X memory Address Bus (XAB), Y memory Address Bus (YAB), and the Program Address Bus (PAB). The Nn and Mn registers are 16-bit registers that are normally used to update the Rn registers, but may be used for data. MOTOROLA DSP56012 User’s Manual 1-11...

  • Page 32: Program Control Unit

    EXTAL and the internal chip phases when the Multiplication Factor (MF) 4. The PLL is unique in that it provides a low power divider on its output, which can reduce or restore the chip operating frequency without losing the PLL lock. 1-12 DSP56012 User’s Manual MOTOROLA...

  • Page 33: On-Chip Emulation (Once) Port

    C formats) after a power-on reset. SPI or I Table 1-3 Interrupt Starting Addresses and Sources Interrupt Interrupt Source Starting Address P:$0000 Hardware RESET P:$0002 Stack Error P:$0004 Trace P:$0006 P:$0008 0–2 IRQA P:$000A 0–2 IRQB P:$000C Reserved MOTOROLA DSP56012 User’s Manual 1-13...
  • Page 34 SAI Right Channel Receiver if RXIL = 1 P: $004A 0–2 SAI Receiver Exception if RXIL = 1 P: $004C Reserved; available for Host Command, see p. B-5–B-6. P: $004E Reserved; available for Host Command, see p. B-5–B-6. 1-14 DSP56012 User’s Manual MOTOROLA...

  • Page 35: Data Memory

    4.25 K 3.5 K 3.5 K Program ROM 15 K 15 K 15 K 15 K X ROM 3.5 K 3.5 K 3.5 K 3.5 K Y ROM 2.0 K 2.0 K 2.0 K 2.0 K MOTOROLA DSP56012 User’s Manual 1-15...

  • Page 36: Memory Configuration Bits

    (see Table 1-3 on page 1-13). These interrupt vectors minimize the overhead associated with servicing an interrupt by immediately executing the appropriate service routine. Each interrupt can be configured to one of three maskable priority levels. 1-16 DSP56012 User’s Manual MOTOROLA...

  • Page 37: Table 1-5 On-Chip Peripheral Memory Map

    SAI TX Control/Status Register (TCS) X:$FFE3 SAI RX1 Data Register (RX1) X:$FFE2 SAI RX0 Data Register (RX0) X:$FFE1 SAI RX Control/Status Register (RCS) X:$FFE0 SAI Baud Rate Control Register (BRC) X:$FFDF DAX Status Register (XSTR) MOTOROLA DSP56012 User’s Manual 1-17...

  • Page 38: Parallel Host Interface (Hi)

    This interface can connect directly to one of two well-known and widely-used synchronous serial buses: the Serial Peripheral Interface (SPI) bus defined by Motorola and the Inter Integrated-circuit Control (I bus defined by Philips. The SHI handles both SPI and I C bus protocols as required from a slave or a single-master device.

  • Page 39: Serial Audio Interface (Sai)

    (consisting of two sub-frames) of audio and non-audio data at a time. However, the DAX data path is double buffered so the next frame data can be stored in the DAX without affecting the frame currently being transmitted (see Section 8, Digital Audio Transmitter). MOTOROLA DSP56012 User’s Manual 1-19...
  • Page 40 Overview DSP56012 Architectural Overview 1-20 DSP56012 User’s Manual MOTOROLA...
  • Page 41 SECTION 2 SIGNAL DESCRIPTIONS MOTOROLA DSP56012 User’s Manual...
  • Page 42 OnCE PORT ........2-19 DSP56012 User’s Manual MOTOROLA...

  • Page 43: Signal Groupings

    Host Interface (HI) Port B Table 2-6 Serial Host Interface (SHI) Table 2-7 Serial Audio Interface (SAI) Table 2-8 Table 2-9 General Purpose Input/Output (GPIO) Table 2-10 Digital Audio Transmitter (DAX) Table 2-11 OnCE Port Table 2-12 MOTOROLA DSP56012 User’s Manual...

  • Page 44: Figure 2-1 Dsp56012 Signals

    SDI1 Rec1 PCAP PINIT SCKT EXTAL SDO0 Tran0 SDO1 Tran1 SDO2 Tran2 MODA/IRQA Interrupt MODB/IRQB /Mode MODC/NMI Control General Purpose GPIO0–GPIO7 RESET Input/Output (GPIO) Digital Audio Transmitter (DAX) DSCK/OS1 OnCE™ DSI/OS0 Port Figure 2-1 DSP56012 Signals DSP56012 User’s Manual MOTOROLA...

  • Page 45: Power

    The user must provide adequate external decoupling capacitors. is an isolated power for the SHI I/O drivers. This Serial Host Power—V input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. MOTOROLA DSP56012 User’s Manual...

  • Page 46: Ground

    SHI I/O drivers. This Serial Host Ground—GND connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. DSP56012 User’s Manual MOTOROLA...

  • Page 47: Phase Lock Loop (Pll)

    PINIT is written into the PLL Enable (PEN) bit of the PLL Control Register, determining whether the PLL is enabled or disabled. EXTAL Input Input External Clock/Crystal Input—EXTAL interfaces the internal crystal oscillator input to an external crystal or an external clock. MOTOROLA DSP56012 User’s Manual...

  • Page 48: Interrupt And Mode Control

    IRQB. After reset, the chip operating mode can be changed by software. The IRQB input is an external interrupt request that indicates that an external device is requesting service. It may be programmed to be level-sensitive or negative-edge-triggered. DSP56012 User’s Manual MOTOROLA...
  • Page 49 MODA, MODB, and MODC signals. The internal reset signal is deasserted synchronous with the internal clocks. In addition, the PINIT pin is sampled and written into the PEN bit of the PLL Control Register. MOTOROLA DSP56012 User’s Manual...

  • Page 50: Host Interface (Hi)

    Host Interface register. PB8–PB10 Input/ Port B GPIO 8–10 (PB8–PB10)—These signals are Output General Purpose I/O signals (PB8–PB10) when the Host Interface is not selected. After reset, the default state for these signals is GPIO input. 2-10 DSP56012 User’s Manual MOTOROLA...
  • Page 51 Input/ Port B GPIO 13 (PB13)—This signal is a General Output Purpose (not open-drain) I/O signal (PB13) when the Host Interface is not selected. After reset, the default state for this signal is GPIO input. MOTOROLA DSP56012 User’s Manual 2-11...
  • Page 52 PB14 Input/ Port B GPIO 14 (PB14)—This signal is a General Output Purpose I/O signal (PB14) when the Host Interface is not selected. After reset, the default state for this signal is GPIO input. 2-12 DSP56012 User’s Manual MOTOROLA...

  • Page 53: Serial Host Interface (Shi)

    EXTAL. The maximum allowed externally generated bit clock frequency is f /3 for the SPI mode and f /5 for the I C mode An external pull-up resistor is not required. MOTOROLA DSP56012 User’s Manual 2-13...
  • Page 54 C mode. When configured for I C Slave mode, the HA0 signal is used to form the slave device address. HA0 is ignored when it is configured for the I C Master mode. An external pull-up resistor is not required. 2-14 DSP56012 User’s Manual MOTOROLA...
  • Page 55 HREQ to proceed to the next transfer. This signal is tri-stated during hardware, software, personal reset, or when the HREQ1–HREQ0 bits in the HCSR are cleared (no need for external pull-up in this state). MOTOROLA DSP56012 User’s Manual 2-15...

  • Page 56: Serial Audio Interface (Sai)

    WSR is high impedance if all receivers are disabled (personal reset), during hardware reset, during software reset, or while the chip is in the stop state. No external pull-up is necessary. 2-16 DSP56012 User’s Manual MOTOROLA...

  • Page 57: Sai Transmit Section

    WST is tri-stated if all transmitters are disabled (personal reset), during hardware or software reset, or while the chip is in the Stop state. No external pull-up is necessary. MOTOROLA DSP56012 User’s Manual 2-17...

  • Page 58: General Purpose Input/Output (Gpio)

    The ACI signal is high impedance (tri-stated) only during hardware or software reset. If the DAX is not used, connect the ACI signal to ground through an external pull-down resistor to ensure a stable logic level at the input. 2-18 DSP56012 User’s Manual MOTOROLA...

  • Page 59: Once Port

    Debug mode. Note: If the OnCE interface is in use, an external pull-down resistor should be attached to this pin. If the OnCE interface is not in use, the resistor is not required. MOTOROLA DSP56012 User’s Manual 2-19...
  • Page 60 Stop or Wait state. Having DR asserted during the deassertion of RESET will cause the DSP to enter Debug mode. Note: If the OnCE interface is not in use, attach an external pull-up resistor to the DR input. 2-20 DSP56012 User’s Manual MOTOROLA...
  • Page 61 SECTION 3 MEMORY, OPERATING MODES, AND INTERRUPTS...
  • Page 62 INTERRUPT PRIORITY REGISTER....3-14 PHASE LOCK LOOP (PLL) CONFIGURATION ..3-18 OPERATION ON HARDWARE RESET ....3-19 DSP56012 User’s Manual MOTOROLA...

  • Page 63: Introduction

    Table 3-1. Note: Internal Data and Program ROMs are factory-programmed to support specific applications. Refer to the DSP56012 Technical Data sheet, order number DSP56012/D, for more information about available configurations. MOTOROLA DSP56012 User’s Manual...

  • Page 64: And Y Data Rom

    Program RAM Enable (PEA and PEB) bits in the OMR. Memory maps for each of the four configurations are shown in Figure 3-1, Figure 3-2, Figure 3-3, and Figure 3-4, on the following pages. DSP56012 User’s Manual MOTOROLA...

  • Page 65: Reserved Memory Spaces

    $000005, which is the opcode for the ILLEGAL instruction. If an instruction fetch is attempted from an address in the reserved area, the value returned is $000005, (ILLEGAL opcode). Figure 3-1 Memory Maps for PEA = 0, PEB = 0 MOTOROLA DSP56012 User’s Manual...
  • Page 66 Memory, Operating Modes, and Interrupts DSP56012 Data and Program Memory Maps Figure 3-2 Memory Maps for PEA = 1, PEB = 0 DSP56012 User’s Manual MOTOROLA...
  • Page 67 Memory, Operating Modes, and Interrupts DSP56012 Data and Program Memory Maps Figure 3-3 Memory Maps for PEA = 0, PEB = 1 MOTOROLA DSP56012 User’s Manual...

  • Page 68: Dynamic Switch Of Memory Configurations

    Specifically, the following two conditions must be observed for trouble-free dynamic switching: • No accesses to or from X:$0A00–$0FFF or Y:$0E00–$10FF are allowed during the switch cycle. DSP56012 User’s Manual MOTOROLA...
  • Page 69 ; Disable interrupts INST1 ; Four instruction cycles guarantee no interrupts INST2 ; after interrupts were disabled. INST3 ; INST# denotes any one-word instruction, however, INST4 ; two one-word instructions can be replaced by ; one two-word instruction. MOTOROLA DSP56012 User’s Manual...

  • Page 70: Internal I/O Memory Map

    Interrupt Priority Register (IPR) X: $FFFE Reserved X: $FFFD PLL Control Register (PCTL) X: $FFFC Reserved X: $FFFB Reserved X: $FFFA Reserved X: $FFF9 Reserved X: $FFF8 Reserved X: $FFF7 GPIO Control/Data Register (GPIOR) X: $FFF6 Reserved 3-10 DSP56012 User’s Manual MOTOROLA...
  • Page 71 SAI RX Control/Status Register (RCS) X: $FFE0 SAI Baud Rate Control Register (BRC) X: $FFDF DAX Status Register (XSTR) X: $FFDE DAX Control Register (XCTR) X: $FFDD Reserved X:$FFDC DAX Transmit Data Registers (XADRA and XADRB) X:$FFDB–FFC0 Reserved MOTOROLA DSP56012 User’s Manual 3-11...

  • Page 72: Operating Mode Register (Omr)

    (SD = 0), a 65,535 core clock cycle delay (131,072 T states) is implemented before continuation of the STOP instruction cycle. If the SD bit is set (SD = 1), the delay before continuation of the STOP instruction cycle is set as eight clock cycles (16 3-12 DSP56012 User’s Manual MOTOROLA...

  • Page 73: Operating Modes

    It is not possible to reach operating Mode 3 during hardware reset. Any attempt to start up in Mode 3 defaults to Mode 1. Mode 4 In this mode, the bootstrap ROM is enabled and the bootstrap program is executed after hardware reset. The bootstrap program MOTOROLA DSP56012 User’s Manual 3-13...
  • Page 74 I C Slave mode, with 24-bit word width. Note: The OnCE port operation is enabled at hardware reset. This means the device can enter the Debug mode at any time after hardware reset. 3-14 DSP56012 User’s Manual MOTOROLA...

  • Page 75: Interrupt Priority Register

    DAX, SAI). Two IPL bits are required for each peripheral interrupt group. The interrupt priorities are shown in Table 3-4 on page 3-16 and the interrupt vectors are shown in Table 3-5 on page 3-17. MOTOROLA DSP56012 User’s Manual 3-15...

  • Page 76: Figure 3-6 Interrupt Priority Register (Addr X:$Ffff)

    Interrupt Level 3 (Nonmaskable) Highest Hardware RESET Illegal Instruction Stack Error Trace Lowest Levels 0, 1, 2 (Maskable) Highest IRQA IRQB SAI Receiver Exception SAI Transmitter Exception SAI Left Channel Receiver SAI Left Channel Transmitter 3-16 DSP56012 User’s Manual MOTOROLA...

  • Page 77: Table 3-5 Interrupt Vectors

    SAI Left Channel Transmitter if TXIL = 0 P: $0012 SAI Right Channel Transmitter if TXIL = 0 P: $0014 SAI Transmitter Exception if TXIL = 0 P: $0016 SAI Left Channel Receiver if RXIL = 0 MOTOROLA DSP56012 User’s Manual 3-17...
  • Page 78 SAI Left Channel Receiver if RXIL = 1 P: $0048 SAI Right Channel Receiver if RXIL = 1 P: $004A SAI Receiver Exception if RXIL = 1 P: $004C Reserved P: $004E Reserved P: $0050 DAX Transmit Underrun Error 3-18 DSP56012 User’s Manual MOTOROLA...

  • Page 79: Phase Lock Loop (Pll) Configuration

    PEN bit is set. This reset value cannot be modified by the user until the DSP comes out of Reset. The DSP56012 LPD Division Factor bits (DF[3:0] in the PCTL) are cleared during hardware reset. Once the PEN bit is set, it cannot be cleared by software. MOTOROLA DSP56012 User’s Manual 3-19...

  • Page 80: Operation On Hardware Reset

    Reset state it: • loads the chip operating mode bits of the OMR from the external mode select pins (MODC, MODB, MODA), and • begins program execution of the bootstrap ROM starting at address $0000. 3-20 DSP56012 User’s Manual MOTOROLA...
  • Page 81 SECTION 4 PARALLEL HOST INTERFACE MOTOROLA DSP56012 User’s Manual...
  • Page 82 PROGRAMMING THE GPIO......4-8 HOST INTERFACE (HI) ......4-9 DSP56012 User’s Manual MOTOROLA...

  • Page 83: Introduction

    Note: Because reset clears both the PBC and PBDDR registers, the default function of the fifteen specified pins following reset is GPIO input. Note: Circuitry connected to the Port B pins may need external pull-ups until the pins are configured for operation. MOTOROLA DSP56012 User’s Manual...

  • Page 84: Figure 4-2 Parallel Port B Registers

    Parallel I/O (Reset Condition) HI (with HACK pin as GPIO) Reserved Port B Data Direction X:$FFED Register (PBDDR) Data Direction Input (Reset Condition) Output Port B Data X:$FFEE Register (PBD) AA0308.11 Figure 4-2 Parallel Port B Registers DSP56012 User’s Manual MOTOROLA...

  • Page 85: Figure 4-3 Port B Gpio Signals And Registers

    BC0/BC1 BC0/BC1 BC0/BC1 BC0/BC1 BC0/BC1 BC0/BC1 PB10 BC0/BC1 BD10 PB10 PB11 BC0/BC1 BD11 PB11 PB12 BC0/BC1 BD12 PB12 PB13 BC0/BC1 BD13 PB13 PB14 BC0/BC1 BD14 PB14 PBDDR AA0309.11 Figure 4-3 Port B GPIO Signals and Registers MOTOROLA DSP56012 User’s Manual...

  • Page 86: Port B Control (Pbc) Register

    HI port. Writing a $2 to the PBC register defines the pins as an HI port without a HACK signal; the pin used by HACK in the HI is defined as a GPIO pin (PB14). DSP56012 User’s Manual MOTOROLA...

  • Page 87: Port B Data Direction Register (Pbddr)

    DSP and the external host properly read status bits transmitted between them. There is more discussion of such port usage issues in Sections 4.4.4.7 HI Usage Considerations—DSP Side and 4.4.8.4 HI Port Usage Considerations—Host Side. MOTOROLA DSP56012 User’s Manual...

  • Page 88: Programming The Gpio

    However, some situations may require programming the data direction or the data registers first to prevent two devices from driving one signal. The order of steps 1, 2, and 3 in Figure 4-6 is optional and can be changed as needed. DSP56012 User’s Manual MOTOROLA...

  • Page 89: Host Interface (Hi)

    DSP Central Processing Unit (CPU) (see Figure 4-7 on page 4-12). Note: Unlike other DSPs in this Motorola family, this device uses the SHI for a host control interface, and the HI as a high-speed parallel data transfer interface.

  • Page 90: Hi Features

    – Memory-mapped registers allow the standard MOVE instruction to be used. – Special MOVEP instruction provides for I/O service capability using fast inter rupts. – Bit addressing instructions (BCHG, BCLR, BSET, BTST, JCLR, JSCLR, JSET, JSSET) simplify I/O service routines. 4-10 DSP56012 User’s Manual MOTOROLA...

  • Page 91: Hi Block Diagram

    DSP on the right. They can also be divided horizontally into control (at the top), DSP-to-host data transfer (in the middle), and host-to-DSP data transfer (at the bottom). MOTOROLA DSP56012 User’s Manual 4-11...

  • Page 92: Hi-Dsp Viewpoint

    Separate transmit and receive data registers are double-buffered to allow the DSP and host processor to transfer data efficiently at high speed. Memory mapping allows communication with the HI registers to use 4-12 DSP56012 User’s Manual MOTOROLA...

  • Page 93: Programming Model-Dsp Viewpoint

    Transmit/Receive register (HOTX/HORX). These registers can only be accessed by the DSP56012; they can not be accessed by the host processor. The HI-to-host processor programming model is presented in Section 4.4.5 HI—Host Processor Viewpoint and is illustrated in Figure 4-10 on page 4-23. MOTOROLA DSP56012 User’s Manual 4-13...

  • Page 94: Hi Control Register (Hcr)

    The HI Control Register (HCR) is an 8-bit read/write control register used by the DSP to control the host interrupts and flags. The HCR cannot be accessed by the host processor. It occupies the low-order byte of the internal data bus; the high-order 4-14 DSP56012 User’s Manual MOTOROLA...

  • Page 95: Hcr Hi Receive Interrupt Enable (Hrie)-Bit 0

    The HI Flag 3 (HF3) bit is used as a general purpose flag for DSP-to-host communication. HF3 can be set or cleared by the DSP. HF3 is visible to the host processor in the ISR (see Figure 4-9 on page 4-18). MOTOROLA DSP56012 User’s Manual 4-15...

  • Page 96: Hcr Reserved-Bits 5, 6, And 7

    RXH:RXM:RXL registers. HTDE is cleared when HOTX is written by the DSP. HTDE can also be set by the host processor using the initialize function. Note: Hardware reset, software reset, individual reset, and Stop mode set HTDE. 4-16 DSP56012 User’s Manual MOTOROLA...

  • Page 97: Hsr Hi Command Pending (Hcp)-Bit 2

    The HI Flag 1 (HF1) bit in the HSR indicates the state of host flag 1 in the ICR (on the host processor side). HF1 can only be changed by the host processor (see Figure 4-9). Note: Hardware reset, software reset, individual reset, and Stop mode clear HF1. MOTOROLA DSP56012 User’s Manual 4-17...

  • Page 98: Hsr Reserved-Bits 5 And 6

    HORX register is viewed as a 24-bit read-only register by the DSP CPU. The HORX register is loaded with 24-bit data from the Transmit data registers (TXH:TXM:TXL) on the host processor side when both the host-side Transmit Data register Empty 4-18 DSP56012 User’s Manual MOTOROLA...

  • Page 99: Hi Transmit Data Register (Hotx)

    (ST) is caused by executing the STOP instruction. Table 4-1 HI Registers after Reset—DSP CPU Side Reset Type Register Register Name Data Reset Reset Reset Reset HF[3:2] — — HCIE — — X:$FFE8 HTIE — — HRIE — — MOTOROLA DSP56012 User’s Manual 4-19...

  • Page 100: Dsp Interrupts

    HI register (clearing HRDF or HTDE, for example) to clear the interrupt. Note: In the case of host command interrupts, the interrupt acknowledge from the program controller clears the pending interrupt condition. 4-20 DSP56012 User’s Manual MOTOROLA...

  • Page 101: Hi Usage Considerations-Dsp Side

    MC6801-type host processors can use 16-bit load (LDD) and store (STD) instructions for data transfers. The 16-bit MC68000/MC68010 host processor can address the HI using the special MOVEP instruction for word (16-bit) or long-word (32-bit) MOTOROLA DSP56012 User’s Manual 4-21...

  • Page 102: Host Command

    DSP56012 registers (X, Y, or program memory locations), force interrupt handlers (e.g., SHI, SAI, DAX, IRQA, IRQB interrupt routines), and perform control and debugging operations, if interrupt routines are implemented in the DSP56012 to perform these tasks. 4-22 DSP56012 User’s Manual MOTOROLA...

  • Page 103: Figure 4-10 Host Processor Programming Model-Host Side

    Receive Low Byte Not Used Transmit High Byte Transmit Middle Byte Transmit Low Byte Transmit Byte Registers (TXH:TXM:TXL) (Write Only) AA0319k Note: The numbers in parentheses are reset initialization values. Figure 4-10 Host Processor Programming Model–Host Side MOTOROLA DSP56012 User’s Manual 4-23...

  • Page 104: Interrupt Control Register (Icr)

    HOREQ pin when the Transmit Data register Empty (TXDE) status bit in the ISR is set. When TREQ is cleared, TXDE interrupts are disabled. When TREQ is set, the external HOREQ pin will be asserted if TXDE is set. 4-24 DSP56012 User’s Manual MOTOROLA...

  • Page 105: Icr Reserved-Bit 2

    DSP. HF0 is visible to the DSP as the read-only flag HF0 in the HSR (see Figure 4-9 on page 4-18). Note: Hardware reset, software reset, individual reset, and Stop mode clear HF0. MOTOROLA DSP56012 User’s Manual 4-25...

  • Page 106: Icr Hi Flag 1 (Hf1)-Bit 4

    HI (see Table 4-3). HM1 and HM0 enable the DMA mode of operation or the Interrupt (non-DMA) mode of operation. Table 4-3 HI Mode Bit Definition Mode Interrupt Mode (DMA Off) DMA Mode (24-bit) DMA Mode (16-bit) DMA Mode (8-bit) 4-26 DSP56012 User’s Manual MOTOROLA...

  • Page 107: Icr Initialize Bit (Init)-Bit 7

    4.4.5.4 HI Initialization There are two methods of initialization: 1. allowing the DMA address counter to be automatically set after transferring a word, and 2. setting the INIT bit, which sets the DMA address counter. MOTOROLA DSP56012 User’s Manual 4-27...

  • Page 108: Table 4-4 Horeq Pin Definition

    (RXL or TXL). When the DMA transfer is completed, the counter is loaded with the value of the HM1 and HM0 bits. When changing the size of the DMA word (changing HM0 and HM1 in the ICR), the DMA 4-28 DSP56012 User’s Manual MOTOROLA...

  • Page 109: Command Vector Register (Cvr)

    Stop mode. Note: The HV should not be used with a value of 0 because the reset location is normally programmed with a JMP instruction. Doing so will cause an improper fast interrupt. MOTOROLA DSP56012 User’s Manual 4-29...

  • Page 110: Cvr Reserved-Bit 6

    Regardless of whether the RXDF interrupt is enabled, RXDF provides valid status so that polling techniques can be used by the host processor. Note: Hardware reset, software reset, individual reset, and Stop mode clear RXDF. 4-30 DSP56012 User’s Manual MOTOROLA...

  • Page 111: Isr Transmit Data Register Empty (Txde)-Bit 1

    DSP changing HF3 in the HCR (see Figure 4-12 on page 4-26). Note: HF3 is cleared by hardware reset and software reset. 4.4.5.6.6 ISR Reserved—Bit 5 This bit is reserved for future expansion and will read as 0 during host processor read operations. MOTOROLA DSP56012 User’s Manual 4-31...

  • Page 112: Isr Host Request (Horeq)-Bit 7

    MC68000 family. 4.4.5.8 Receive Byte Registers (RXH, RXM, RXL) The receive byte registers are viewed by the host processor as three 8-bit read-only registers. These registers are called Receive High (RXH), Receive Middle (RXM), and 4-32 DSP56012 User’s Manual MOTOROLA...

  • Page 113: Transmit Byte Registers (Txh, Txm, Txl)

    The hardware reset is caused by asserting the RESET pin; the software reset is caused by executing the RESET instruction; the individual reset is caused by clearing the PBC register bit 0; and the stop reset is caused by executing the STOP instruction. MOTOROLA DSP56012 User’s Manual 4-33...

  • Page 114: Table 4-5 Hi Registers After Reset (Host Side)

    — — — — — (23–16) RXM (15–8) — — — — RXL (7–0) — — — — — — — — (23–21) TXM (15–8) — — — — TXL (7–0) — — — — 4-34 DSP56012 User’s Manual MOTOROLA...

  • Page 115: Hi Signals

    The Host Request (HOREQ) open-drain output signal is used by the DSP56012 HI to request service from the host processor, DMA controller, or simple external controller. HOREQ can be connected to an interrupt request pin of a host processor, a MOTOROLA DSP56012 User’s Manual 4-35...

  • Page 116: Host Acknowledge (Hack)

    HI is not affected. Table 4-6 Port B Pin Definitions Function Parallel I/O (Reset Condition) HI (HACK is defined as GPIO) Reserved Note: HACK should always be pulled high when it is not in use. 4-36 DSP56012 User’s Manual MOTOROLA...

  • Page 117: Servicing The Hi

    The HI looks like Static RAM to the host processor. Accordingly, in order to transfer data with the HI, the host processor: 1. asserts the Host Address (HOA[2:0]) to select the register to be read or written; 2. asserts HR/W to select the HI for the current access, and MOTOROLA DSP56012 User’s Manual 4-37...

  • Page 118: Host Interrupts Using Host Request (Horeq)

    DSP side. 4. HF2 HF3 0, signifying that an application-specific state within the DSP CPU has been reached, and requires action on the part of the host processor. 4-38 DSP56012 User’s Manual MOTOROLA...

  • Page 119: Servicing Non-Dma Interrupts

    HOREQ pins from other DSP56012 processors in the system. When the DSP56012 generates an interrupt request, the host processor can poll the HOREQ bit in the ISR of each of the connected DSPs to determine which device generated the interrupt. MOTOROLA DSP56012 User’s Manual 4-39...

  • Page 120: Figure 4-15 Interrupt Vector Register Read Timing

    IVR are placed on the host data bus. (IVR) H0–H7 D0–D7 AA0323.11 Figure 4-15 Interrupt Vector Register Read Timing Status interrupt Source HF2 TRDY TXDE RXDF HOREQ HOREQ Asserted HOREQ INIT TREQ RREQ AA0324k Mask Figure 4-16 HI Interrupt Structure 4-40 DSP56012 User’s Manual MOTOROLA...

  • Page 121: Servicing Dma Interrupts

    HACK is used to strobe the data transfer, as shown in Figure 4-17 on page 4-41 where an MC68440 is used as the DMA controller. DMA transfers to and from the HI are presented in more detail in Section 4.4.8 Host Interface Application Examples. MOTOROLA DSP56012 User’s Manual 4-41...

  • Page 122: Host Interface Application Examples

    2) PBC at X:$FFE0 STEP 2 The Host Processor initializes the host side of the HI by writing: 1) ICR at $0 and/or 2) CVR at $1 and/or 3) IVR at $3 AA0326k Figure 4-18 HI Initialization Flowchart 4-42 DSP56012 User’s Manual MOTOROLA...

  • Page 123: Figure 4-19 Hi Initialization-Dsp Side

    6.Select Port B For HI Port Operation: X:$FFEC Reserved; write as 0. Note: The host flags are general-purpose semaphores. They are not required for host port operation but can be used in some applications. AA0327 Figure 4-19 HI Initialization—DSP Side MOTOROLA DSP56012 User’s Manual 4-43...

  • Page 124: Figure 4-20 Hi Initialization-Host Side, Interrupt Mode

    2. Option 4: Load HI Interrupt vector if using the interrupt mode and the host processor requires an interrupt vector. Interrupt Vector Register (IVR) (Read/Write) Reserved; write as 0 AA0328k Figure 4-20 HI Initialization—Host Side, Interrupt Mode 4-44 DSP56012 User’s Manual MOTOROLA...

  • Page 125: Polling/Interrupt Controlled Data Transfer

    DSP as fast memory, and data can be transferred between the host and DSP at the fastest host processor rate. DMA hardware can be used with the external host request and host acknowledge pins to transfer data at the maximum DSP interrupt rate. MOTOROLA DSP56012 User’s Manual 4-45...

  • Page 126: Figure 4-22 Hi Initialization-Host Side, Polling Mode

    2. Assert HACK (if the interface is using HACK). 3. Assert HR/W to select whether this operation will read or write a register. 4. Assert the HI address (HOA2, HOA1, HOA0) to select the register to be read or written. 4-46 DSP56012 User’s Manual MOTOROLA...

  • Page 127: Figure 4-24 Hi Initialization-Host Side, Dma Mode

    Bit 1 = 1 Bit 5 = 1 Optional Bit 6 = 1 INTERRUPT CONTROL REGISTER (ICR) INIT TREQ RREQ (read/write) *See Figure 4-26. Reserved; write as 0 AA0332k Figure 4-24 HI Initialization–Host Side, DMA Mode MOTOROLA DSP56012 User’s Manual 4-47...
  • Page 128 Parallel Host Interface Host Interface (HI) 4-48 DSP56012 User’s Manual MOTOROLA...

  • Page 129: Host To Dsp-Data Transfer

    9. The DSP can poll HRDF to see when data has arrived, or it can use interrupts. 10. If HRIE (in the HCR) and HRDF are set, interrupt processing is started using interrupt vector P:$0030. MOTOROLA DSP56012 User’s Manual 4-49...
  • Page 130 Parallel Host Interface Host Interface (HI) 4-50 DSP56012 User’s Manual MOTOROLA...

  • Page 131: Host To Dsp-Command Vector

    P:$0040–$004A, which are reserved for SAI interrupts, or addresses $P:$0050, $0052, and $0056, which are reserved for DAX interrupts. In other words, when using these peripherals, restrict the HC to the following interrupt vector addresses: P:$0034–$003C, $004C–$004E, $0054, and $0058–007E. MOTOROLA DSP56012 User’s Manual 4-51...
  • Page 132 Parallel Host Interface Host Interface (HI) 4-52 DSP56012 User’s Manual MOTOROLA...

  • Page 133: Figure 4-28 Receive Data From Host-Main Program

    HV can be programmed to any interrupt vector, it is not recommended that HV = 0 (RESET) be used because it does not reset the DSP hardware. DMA must be disabled to use the host interrupt. MOTOROLA DSP56012 User’s Manual 4-53...

  • Page 134: Host To Dsp-Bootstrap Loading Using The Hi

    Low Byte Low Byte Initiates Transfer 24 23 16 15 Read—00000000 Host High Middle Write—XXXXXXXX Data 8-bit Transfer 16-bit Transfer 24-bit Transfer 32-bit Transfer, Lowest 24 Bits Are Significant AA0338k Figure 4-30 Transmit/Receive Byte Registers 4-54 DSP56012 User’s Manual MOTOROLA...

  • Page 135: Figure 4-31 Bootstrap Using The Host Interface

    7P:$01FF Low BYTE • Because the DSP56012 is so fast, host handshaking is generally not required. AA0337k Figure 4-31 Bootstrap Using the Host Interface The actual code used in the bootstrap program is provided in Appendix A. MOTOROLA DSP56012 User’s Manual 4-55...

  • Page 136: Dsp To Host-Data Transfer

    (RXH:RXM:RXL). This transfer sets RXDF in the ISR (7), which the host processor can poll to see if data is available or, if the RREQ bit in the ICR is set, the HI will interrupt the host processor with HOREQ (8). 4-56 DSP56012 User’s Manual MOTOROLA...
  • Page 137 Parallel Host Interface Host Interface (HI) MOTOROLA DSP56012 User’s Manual 4-57...
  • Page 138 Parallel Host Interface Host Interface (HI) 4-58 DSP56012 User’s Manual MOTOROLA...

  • Page 139: Dma Data Transfer

    DMA transfer by deasserting HACK and using HEN and HOA0–HOA2 to transfer data. The host can therefore transfer data in the other direction during the DMA operation using polling techniques. MOTOROLA DSP56012 User’s Manual 4-59...

  • Page 140: Figure 4-35 Hi Hardware-Dma Mode

    • Host processor software polled transfers are permitted in the opposite direction of the DMA transfer. • 8-, 16-, or 24-bit transfers are supported. • 16-, or 24-bit transfers reduce the DSP interrupt rate by a factor of 2 or 3, respectively. AA0341k Figure 4-35 HI Hardware–DMA Mode 4-60 DSP56012 User’s Manual MOTOROLA...

  • Page 141: Host To Dsp-Internal Processing

    TXH:TXM:TXL are transferred to HORX (provided that HRDF = 0). After the transfer to HORX, TXDE will be set, and HOREQ will be asserted to start the transfer of another word from external memory to the HI. MOTOROLA DSP56012 User’s Manual 4-61...

  • Page 142: Host To Dsp-Dma Procedure

    TXH, TXM and TXL registers can not be accessed until the DMA mode is disabled. 5. Terminate the DMA controller channel (8) to disable DMA transfers. 6. Terminate the DSP-to-DMA mode (9) in the ICR by clearing the HM1 and HM0 bits and clearing TREQ. 4-62 DSP56012 User’s Manual MOTOROLA...
  • Page 143 Parallel Host Interface Host Interface (HI) MOTOROLA DSP56012 User’s Manual 4-63...

  • Page 144: Dsp To Hi -Internal Processing

    Note: The transfer of data from the HOTX register to the RXH:RXM:RXL registers automatically loads the DMA address counter from the HM1 and HM0 bits when in the DMA DSP-Host mode. This DMA address is used within the HI to place the appropriate byte on H[0:7]. 4-64 DSP56012 User’s Manual MOTOROLA...

  • Page 145: Dsp To Host-Dma Procedure

    When reading receive byte registers, RXH, RXM, or RXL, the host programmer should use interrupts or poll the RXDF flag which indicates that data is available. This guarantees that the data in the receive byte registers will be stable. MOTOROLA DSP56012 User’s Manual 4-65...

  • Page 146: Overwriting Transmit Byte Registers

    HC bit is cleared because the host processor does not know exactly when the interrupt will be recognized. This uncertainty in timing is due to differences in synchronization between the host processor and DSP CPU and the 4-66 DSP56012 User’s Manual MOTOROLA...

  • Page 147: Coordinating Data Transfers

    For example, HEN is capable of reacting to a 2 ns noise spike when not terminated. Allowing HACK to float can cause problems even though it is not needed in a circuit. MOTOROLA DSP56012 User’s Manual 4-67...
  • Page 148 Parallel Host Interface Host Interface (HI) 4-68 DSP56012 User’s Manual MOTOROLA...
  • Page 149 SECTION 5 SERIAL HOST INTERFACE MOTOROLA DSP56012 User’s Manual...
  • Page 150 CHARACTERISTICS OF THE I2C BUS ....5-20 SHI PROGRAMMING CONSIDERATIONS ... . 5-23 DSP56012 User’s Manual MOTOROLA...

  • Page 151: Introduction

    The SHI can also communicate with other serial peripheral devices. The SHI can interface directly to either of two well-known and widely used synchronous serial buses: the Motorola Serial Peripheral Interface (SPI) bus and the Philips Inter-Integrated-circuit Control (I C) bus.

  • Page 152: Serial Host Interface Internal Architecture

    Global Clock Data Generator SCK/SCL HCKR HCSR MISO/SDA Controller Logic MOSI/HA0 Control INPUT/OUTPUT Shift Register Logic (IOSR) SS/HA2 HREQ (FIFO) Slave Address Recognition Unit (SAR) HSAR 24 BIT AA0416 Figure 5-1 Serial Host Interface Block Diagram DSP56012 User’s Manual MOTOROLA...

  • Page 153: Shi Clock Generator

    • Host side—see Figure 5-3 below and Section 5.4.1 on page 5-8 • DSP side—see Figure 5-4 on page 5-6 and Sections 5.4.2 on page 5-8 through 5.4.6 on page 5-13 for detailed information I/O Shift Register (IOSR) IOSR AA0418 Figure 5-3 SHI Programming Model—Host Side MOTOROLA DSP56012 User’s Manual...
  • Page 154 Serial Host Interface Serial Host Interface Programming Model DSP56012 User’s Manual MOTOROLA...

  • Page 155: Table 5-1 Shi Interrupt Vectors

    SHI Bus Error Table 5-2 SHI Internal Interrupt Priorities Priority Interrupt Highest SHI Bus Error SHI Receive Overrun Error SHI Transmit Underrun Error SHI Receive FIFO Full SHI Transmit Data Lowest SHI Receive FIFO Not Empty MOTOROLA DSP56012 User’s Manual...

  • Page 156: Shi Input/Output Shift Register (Iosr)-Host Side

    In the single-byte data transfer mode the most significant byte of the HTX is transmitted; in the double-byte mode the two most significant bytes, and in the triple-byte mode all the HTX is transferred. DSP56012 User’s Manual MOTOROLA...

  • Page 157: Shi Host Receive Data Fifo (Hrx)-Dsp Side

    The SHI Clock Control Register (HCKR) is a 24-bit read/write register that controls the SHI clock generator operation. The HCKR bits should be modified only while the SHI is in the individual reset state (HEN = 0 in the HCSR). MOTOROLA DSP56012 User’s Manual...

  • Page 158: Clock Phase And Polarity (Cpha And Cpol)-Bits

    Figure 5-6 SPI Data-To-Clock Timing Diagram The Clock Phase (CPHA) bit controls the relationship between the data on the MISO and MOSI pins and the clock produced or received at the SCK pin. This control bit is 5-10 DSP56012 User’s Manual MOTOROLA...

  • Page 159: Hckr Prescaler Rate Select (Hrs)-Bit 2

    The HRS bit controls a prescaler in series with the clock generator divider. This bit is used to extend the range of the divider when slower clock rates are desired. When HRS is set, the prescaler is bypassed. When HRS is cleared, the fixed divide-by-eight MOTOROLA DSP56012 User’s Manual 5-11...

  • Page 160: Hckr Divider Modulus Select (Hdm[5:0])-Bits 8-3

    When HFM1 = 1 and HFM0 = 1, the wide-spike-tolerance filter mode is selected. In this mode the filters eliminate spikes up to 100 ns. This mode is recommended for use 5-12 DSP56012 User’s Manual MOTOROLA...

  • Page 161: Shi Control/Status Register (Hcsr)-Dsp Side

    C is cleared, the SHI operates in the SPI mode. When HI C is set, the SHI operates in the I C mode. HI C affects the functionality of the SHI pins as described in Section 2 Pin Descriptions. It is recommended that an SHI individual MOTOROLA DSP56012 User’s Manual 5-13...

  • Page 162: Hcsr Serial Host Interface Mode (Hm[1:0])-Bits

    Section 5.4.6.17 Host Bus Error (HBER)—Bit 21). When configured as an I C Master, the SHI controls the I C bus by generating start events, clock pulses, and stop events for transmission and reception of serial data. It is 5-14 DSP56012 User’s Manual MOTOROLA...

  • Page 163: Hcsr Host-Request Enable (Hrqe[1:0])-Bits 8-7

    ACK on the last byte. As a result, the slave transmitter must release the SDA line to allow the master to generate the stop event. If the SHI completes receiving a word and the HRX FIFO is full, the clock will be MOTOROLA DSP56012 User’s Manual 5-15...

  • Page 164: Hcsr Bus-Error Interrupt Enable (Hbie)-Bit 10

    HRNE and HRFF (bits 17 and 19, see below) status bits must be polled to determine if there is data in the receive FIFO. If HRIE[1:0] are not cleared, receive interrupts will be generated according to Table 5-6. 5-16 DSP56012 User’s Manual MOTOROLA...

  • Page 165: Hcsr Host Transmit Underrun Error (Htue)-Bit 14

    DSP. HTDE is set when the data word is transferred from HTX to the shift register, except for a special case in SPI Master mode when CPHA = 0 (see HCKR). When operating in the SPI Master mode with MOTOROLA DSP56012 User’s Manual 5-17...

  • Page 166: Host Receive Overrun Error (Hroe)-Bit 20

    SS is asserted; in this case, transmission is suspended at the end of transmission of the current word. HBER is cleared only by hardware reset, software reset, SHI individual reset, and during the Stop state. 5-18 DSP56012 User’s Manual MOTOROLA...

  • Page 167: Hcsr Host Busy (Hbusy)—Bit 22

    SS line should be held high. If the SS line is driven low when the SHI is in SPI Master mode, a bus error will be generated (the HCSR HBER bit will be set). MOTOROLA DSP56012 User’s Manual 5-19...

  • Page 168: Characteristics Of The I

    (see Figure 5-8). • Stop data transfer—The stop event is defined as a change in the state of the data line, from low to high, while the clock is high (see Figure 5-8). 5-20 DSP56012 User’s Manual MOTOROLA...

  • Page 169: Figure 5-8 I 2 C Start And Stop Events

    “slaves”. A master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave device. In this case the transmitter must leave the data line high to enable the master MOTOROLA DSP56012 User’s Manual 5-21...

  • Page 170: C Data Transfer Formats

    No ACK Slave Device Master Device from Master Device Slave Address Data Byte Last Data Byte N = 0 to M Start Data Bytes Stop AA0426 Figure 5-11 I C Bus Protocol For Host Read Cycle 5-22 DSP56012 User’s Manual MOTOROLA...

  • Page 171: Shi Programming Considerations

    If a write to HTX occurs, its contents are transferred to IOSR between data word transfers. The IOSR data is shifted out (via MISO) and received data is shifted in (via MOSI). The DSP may write HTX if the HTDE status bit is set. If no writes to HTX MOTOROLA DSP56012 User’s Manual 5-23...

  • Page 172: Spi Master Mode

    GPIO pin connected to its SS pin. However, the SS input pin of the SPI master device should be held deasserted (high) for proper operation. If the SPI master device SS pin is asserted, the Host Bus Error status bit (HBER) is set. If the 5-24 DSP56012 User’s Manual MOTOROLA...

  • Page 173: I 2 C Slave Mode

    The HRX FIFO contains valid receive data, which may be read by the DSP, if the HRNE status bit is set. Note: Motorola recommends that an SHI individual reset (HEN cleared) be generated before beginning data reception in order to reset the receive FIFO to its initial (empty) state, such as when switching from transmit to receive data.

  • Page 174: Receive Data In I 2 C Slave Mode

    The HREQ line may be used to interrupt the external I C master device. Connecting the HREQ line between two SHI-equipped DSPs, one operating as an I C master device and the other as an I slave device, enables full hardware handshaking. 5-26 DSP56012 User’s Manual MOTOROLA...

  • Page 175: Transmit Data In I 2 C Slave Mode

    C = 1) and selecting the Master mode of operation (HMST = 1). Before enabling the SHI as an I C master, the programmer should program the appropriate clock rate in HCKR. When configured in the I C Master mode, the SHI external pins operate as follows: MOTOROLA DSP56012 User’s Manual 5-27...
  • Page 176 When deasserted, HREQ will prevent the clock generation of the next data word transfer until it is asserted again. Connecting the HREQ line between two SHI-equipped 5-28 DSP56012 User’s Manual MOTOROLA...

  • Page 177: Receive Data In I C Master Mode

    HTX contents are transferred to the IOSR when the complete word (according to HM0–HM1) has been shifted out. It is, therefore, the responsibility of the programmer to select the right number of bytes in an I C frame so that they fit in a MOTOROLA DSP56012 User’s Manual 5-29...

  • Page 178: Shi Operation During Stop

    • The HCSR status bits and the transmit/receive paths are reset to the same state produced by hardware reset or software reset. • The HCSR and HCKR control bits are not affected. Note: Motorola recommends that the SHI be disabled before entering the Stop state. 5-30 DSP56012 User’s Manual...
  • Page 179 SECTION 6 SERIAL AUDIO INTERFACE MOTOROLA DSP56012 User’s Manual...
  • Page 180 INTRODUCTION ........6-3 SERIAL AUDIO INTERFACE INTERNAL ARCHITECTURE 6-4 SERIAL AUDIO INTERFACE PROGRAMMING MODEL . . . 6-8 PROGRAMMING CONSIDERATIONS ....6-24 DSP56012 User’s Manual MOTOROLA...

  • Page 181: Introduction

    • Maximum external serial clock rate equal to one third of the DSP core clock • Separate transmit and receive sections • Master or Slave operating modes • Three synchronized data transmission lines • Two synchronized data reception lines • Double-buffered MOTOROLA DSP56012 User’s Manual...

  • Page 182: Serial Audio Interface Internal Architecture

    RMST = 0 RClock SCKR RMST = 1 Internal Clock RMST Prescale Divider Divide Divide By 1 Divide By 1 By 2 Divide By 8 Divide By 256 AA0427k PM0–PM7 Figure 6-1 SAI Baud-Rate Generator Block Diagram DSP56012 User’s Manual MOTOROLA...

  • Page 183: Receive Section Overview

    32 bits. This is done by disabling eight data shifts at the beginning/end of the data word transfer, according to the RDWT bit in the RCS register. These shift registers cannot be directly accessed by the DSP. MOTOROLA DSP56012 User’s Manual...

  • Page 184: Sai Transmit Section Overview

    TRDE and TLDE are cleared, and the transmit section external pins, Word Select Transmit (WST) and Serial Clock Transmit (SCKT), are tri-stated. The transmitter section is illustrated in Figure 6-3. DSP56012 User’s Manual MOTOROLA...

  • Page 185: Figure 6-3 Sai Transmit Section Block Diagram

    This is done by enabling eight data shifts at the beginning/end of the data word transfer, according to the TDWE bit in the TCS register. These shift registers cannot be directly accessed by the DSP. MOTOROLA DSP56012 User’s Manual...

  • Page 186: Serial Audio Interface Programming Model

    RXIL bit in the Receive Control Status (RCS) register. The interrupt vector locations for the SAI are shown in Table 6-1. The interrupts generated by the SAI are prioritized as shown in Table 6-2. DSP56012 User’s Manual MOTOROLA...

  • Page 187: Baud Rate Control Register (Brc)

    When read by the DSP, the BRC appears on the two low-order bytes of the 24-bit word, and the high-order byte is read as 0s. The BRC is cleared during hardware reset and software reset. MOTOROLA DSP56012 User’s Manual...

  • Page 188: Prescale Modulus Select (Pm[7:0])-Bits 7-0

    The read/write Receiver 0 Enable (R0EN) control bit enables the operation of SAI Receiver 0. When R0EN is set, Receiver 0 is enabled. When R0EN is cleared, Receiver 0 is disabled. If both R0EN and R1EN are cleared, the receiver section is disabled, 6-10 DSP56012 User’s Manual MOTOROLA...

  • Page 189: Rcs Receiver 1 Enable (R1En)-Bit 1

    16 Most Significant Bits of the receive data register, independent of the Receiver data shift Direction bit (RDIR, see below), while the 8 Least Significant Bits of the receive data register are cleared. If a 32-bit word length is selected, 8 bits are MOTOROLA DSP56012 User’s Manual 6-11...

  • Page 190: Rcs Receiver Data Shift Direction (Rdir)-Bit 6

    WSR low identifies the right data word (see Figure 6-6). The RLRS bit is cleared during hardware reset and software reset. RLRS = 0 Right Left Left Right RLRS = 1 AA0432 Figure 6-6 Receiver Left/Right Selection (RLRS) Programming 6-12 DSP56012 User’s Manual MOTOROLA...

  • Page 191: Rcs Receiver Clock Polarity (Rckp)-Bit 8

    WSR occurs one serial clock cycle earlier (together with the last bit of the previous data word), as required by the I S format (see Figure 6-8). The RREL bit is cleared during hardware reset and software reset. MOTOROLA DSP56012 User’s Manual 6-13...

  • Page 192: Rcs Receiver Data Word Truncation (Rdwt)-Bit 10

    1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 SCKR Left Right RDWT = 0 RDWT = 1 AA0435k Figure 6-9 Receiver Data Word Truncation (RDWT) Programming 6-14 DSP56012 User’s Manual MOTOROLA...

  • Page 193: Rcs Receiver Interrupt Enable (Rxie)-Bit 11

    Channel Receiver, the Right Channel Receiver and the Receiver Exception interrupt vectors are located in program addresses $46, $48, and $4A, respectively. The RXIL bit is cleared during hardware reset and software reset. Refer to Table 6-1 on page 6-9. MOTOROLA DSP56012 User’s Manual 6-15...

  • Page 194: Rcs Receiver Left Data Full (Rldf)-Bit 14

    RXIE is set, an interrupt request will be issued when RRDF is set. The vector of the interrupt request will depend on the state of the receive overrun condition. The RRDF bit is cleared during hardware reset and software reset. 6-16 DSP56012 User’s Manual MOTOROLA...

  • Page 195: Sai Receive Data Registers (Rx0 And Rx1)

    SDO1 line is set to high level. If T0EN, T1EN and T2EN are cleared, the SAI transmitter section is disabled and enters the individual reset state. The T1EN bit is cleared during hardware reset and software reset. MOTOROLA DSP56012 User’s Manual 6-17...

  • Page 196: Tcs Transmitter Master (Tmst)-Bit 3

    When TDIR is cleared, transmit data is shifted out MSB first. When TDIR is set, the data is shifted out LSB first (see Figure 6-10). The TDIR bit is cleared during hardware reset and software reset. 6-18 DSP56012 User’s Manual MOTOROLA...

  • Page 197: Tcs Transmitter Left Right Selection (Tlrs)-Bit 7

    SDOx lines change synchronously with the positive edge of the clock, and are considered valid during negative transitions of the clock (see Figure 6-12). The TCKP bit is cleared during hardware reset and software reset. MOTOROLA DSP56012 User’s Manual 6-19...

  • Page 198: Tcs Transmitter Relative Timing (Trel)-Bit 9

    The read/write Transmitter Data Word Expansion (TDWE) control bit selects the method used to expand a 24-bit data word to 32 bits during transmission. When TDWE is cleared, after transmitting the 24-bit data word from the transmit data 6-20 DSP56012 User’s Manual MOTOROLA...

  • Page 199: Figure 6-14 Transmitter Data Word Expansion (Tdwe) Programming

    TRDE = 1. The transmit data registers should be loaded with the right data words. 3. Transmit interrupt with exception (underrun) is generated when TXIE = 1, TLDE = 1, and TRDE = 1. This means that old data is being retransmitted. MOTOROLA DSP56012 User’s Manual 6-21...

  • Page 200: Tcs Transmitter Interrupt Location (Txil)-Bit 12

    TCS register, followed by writing the transmit data registers of the enabled transmitters. If TXIE is set, an interrupt request will be issued when TLDE is set. The vector of the interrupt request will depend on the state of the transmit underrun 6-22 DSP56012 User’s Manual MOTOROLA...

  • Page 201: Tcs Transmitter Right Data Empty (Trde)-Bit 15

    The transmit data registers should be written with left channel and right channel data alternately. The first word to be transmitted, after enabling the operation of the respective transmitter, will be the left channel word. MOTOROLA DSP56012 User’s Manual 6-23...

  • Page 202: Programming Considerations

    When the condition arises for the receive interrupt to occur, the same interrupt service routine may be used to read data from the receiver section and to write data to the transmitter section. 6-24 DSP56012 User’s Manual MOTOROLA...

  • Page 203: Sai State Machine

    During a data word transfer (i.e., before completion), all transitions in WSR/WST are ignored. After completion of a data word transfer the SAI stops shifting data in and out until the next correct WSR/WST transition is detected. MOTOROLA DSP56012 User’s Manual 6-25...
  • Page 204 WSR/WST transition, the data bits being received are ignored and no data is transmitted. These characteristics can be used to disable reception or transmission of undesired data words by keeping SCKR (SCKT) running freely and gating WSR/WST for a certain number of bit-clock cycles. 6-26 DSP56012 User’s Manual MOTOROLA...
  • Page 205 SECTION 7 GPIO MOTOROLA DSP56012 User’s Manual...
  • Page 206 GPIO PROGRAMMING MODEL ..... . 7-3 GPIO REGISTER (GPIOR) ......7-3 DSP56012 User’s Manual MOTOROLA...

  • Page 207: Introduction

    GPIOR are used to read from or write to the GPIO pins. Hardware reset and software reset clear all the bits in GPIOR. The GPIOR bits are described in the following paragraphs. MOTOROLA DSP56012 User’s Manual...

  • Page 208: Gpior Data Bits (Gd[7:0])-Bits 7-0

    The read/write GPIO Control bits (GC[7:0]) select the type of output buffer for each of the GPIO[7:0] pins when the pins are defined as outputs, and select whether or not the input buffer is connected to the pin when the pin is defined as an input. DSP56012 User’s Manual MOTOROLA...

  • Page 209: Figure 7-2 Gpio Circuit Diagram

    GPIOx pin output buffer is defined as an open-drain type (see Table 7-1 and Figure 7-2). The GC[7:0] bits are cleared during hardware reset and software reset. Buffer GD0–GD7 Control* See Table 7-1 GPIO Pin Configuration. AA0442k Figure 7-2 GPIO Circuit Diagram MOTOROLA DSP56012 User’s Manual...
  • Page 210 GPIO GPIO Register (GPIOR) DSP56012 User’s Manual MOTOROLA...
  • Page 211 SECTION 8 DIGITAL AUDIO TRANSMITTER MOTOROLA DSP56012 User’s Manual...
  • Page 212 DAX INTERNAL ARCHITECTURE ....8-6 DAX PROGRAMMING CONSIDERATIONS ... . 8-14 DSP56012 User’s Manual MOTOROLA...

  • Page 213: Overview

    “polling” technique. A block diagram of the DAX is shown in Figure 8-1. Note: The shaded registers in Figure 8-1 are directly accessible by DSP instructions. MOTOROLA DSP56012 User’s Manual...

  • Page 214: Dax Signals

    (256 Fs, 384 Fs, or 512 Fs). The ACI pin is high impedance during hardware reset and software reset. Note: If the DAX is not used, connect the ACI pin to ground through an external pull-down resistor to ensure a stable logic level at the input. DSP56012 User’s Manual MOTOROLA...

  • Page 215: Dax Functional Overview

    The parity generator calculates an even parity over the 27 bits of audio and non-audio data, and then outputs the result through the biphase encoder to the ADO pin at the last two time slots. This is the end of the first (Channel A) sub-frame transmission. MOTOROLA DSP56012 User’s Manual...

  • Page 216: Dax Programming Model

    DAX Transmit Underrun Error DAX Block Transferred lowest DAX Transmit Register Empty DAX INTERNAL ARCHITECTURE Hardware components shown in Figure 8-1 on page 8-4 are described in the following sub-sections. The DAX programming model is illustrated in Figure 8-2. DSP56012 User’s Manual MOTOROLA...

  • Page 217: Dax Audio Data Registers A And B (Xadra/Xadrb)

    XADBUF is transferred to the XADSR at the beginning of the Channel B transmission. This double buffering mechanism provides more cycles to write the next audio data to XADRA and XADRB. This register is not directly accessible by DSP instructions. MOTOROLA DSP56012 User’s Manual...

  • Page 218: Dax Audio Data Shift Register (Xadsr)

    DAX (by clearing XEN) stops the frame transmission immediately. When this bit is set, disabling the DAX is done at the next frame boundary after finishing the current frame transmission. Note: This bit is cleared by software reset and hardware reset. DSP56012 User’s Manual MOTOROLA...

  • Page 219: Dax Clock Input Select (Xcs[1:0])-Bits 3-4

    The value of the XVB bit is transmitted as the twenty-ninth bit (Bit 28) of the Channel B sub-frame in the next frame. Note: This bit is not affected by any of the DAX reset states. MOTOROLA DSP56012 User’s Manual...

  • Page 220: Dax Channel B User Data (Xub)-Bit 14

    However, it causes a change in the interrupt vector that is sent to DSP core, if an interrupt is generated. This allows programmers to write an exception handling routine for this special case. 8-10 DSP56012 User’s Manual MOTOROLA...

  • Page 221: Dax Block Transfer Flag (Xblk)-Bit 3

    DAX is enabled (XEN = 1). It is cleared either immediately (by clearing the XEN bit, when XSTP = 0), or it is cleared at the next frame boundary (if XSTP = 1). Note: Software reset, hardware reset, and the Stop state clear XTIP immediately. MOTOROLA DSP56012 User’s Manual 8-11...

  • Page 222: Dax Non-Audio Data Buffer (Xnadbuf)

    Table 8-4. The preamble bits are already in the biphase mark format. Table 8-4 Preamble Bit Patterns Preamble Bit Pattern Channel 00011101 00011011 00010111 A (first in block) 8-12 DSP56012 User’s Manual MOTOROLA...

  • Page 223: Dax Clock Multiplexer

    Figure 8-5 shows how each clock is divided to generate the biphase and bit shift clocks. DSP Core Clock (1024 ACI Pin Biphase {256,384,512} Clock (128 Bit Shift (XCS1 or XCS0) Clock XCS1 XCS0 AA0610 Figure 8-5 Clock Multiplexer Diagram MOTOROLA DSP56012 User’s Manual 8-13...

  • Page 224: Dax State Machine

    Within the routine, the next audio data can be stored in the XADRA/XADRB registers, and the next non-audio data can also be stored in the XCTR. 8-14 DSP56012 User’s Manual MOTOROLA...

  • Page 225: Dax Operation During Stop

    No DAX control bits are affected. It is recommended that the DAX be disabled, by clearing the XEN bit in the XCTR, before the DSP enters the Stop state. MOTOROLA DSP56012 User’s Manual 8-15...
  • Page 226 Digital Audio Transmitter DAX Programming Considerations 8-16 DSP56012 User’s Manual MOTOROLA...
  • Page 227 APPENDIX A BOOTSTRAP ROM CONTENTS 0100101001011010 1010101010110110 1010101010010111 0100101001011010 0101001010010111 1010101010110110 1000101010100100 1010101010010111 0100010101011101 0101001010010111 1000101010100100 0100010101011101 MOTOROLA DSP56012 User’s Manual...

  • Page 228: Introduction

    BOOTSTRAPPING THE DSP ......A-3 BOOTSTRAP PROGRAM LISTING ....A-4 DSP56012 User’s Manual MOTOROLA...
  • Page 229 P:$0. The MB bit value selects the protocol under which data is loaded: – MB = 0—The SHI uses the SPI protocol. (Mode 5) – MB = 1—The SHI uses the I C protocol. (Mode 7) MOTOROLA DSP56012 User’s Manual...

  • Page 230: Motorola

    Bootstrap ROM Contents BOOTSTRAP PROGRAM LISTING ; BOOTSTRAP CODE FOR DSP56012—(C) Copyright 1997 Motorola Inc. ; Revised August 28, 1997. ; bootstrap through HOST, SHI-SPI and SHI-I2C,according to op-modes MC:MB:MA. comment _________ RESET Wake up on bootstrap mode \_________/ with OnCE port enabled...
  • Page 231 #hf0,x:hsr,_LBLB ; if HF0 = 1, stop loading data enddo ; must terminate the loop <_loop1 _LBLB jclr #hrdf,x:hsr,_LBLA ; wait for data present movep x:horx,p:(r0)+ ; store in Program RAM _loop1 <exit ; Exit bootstrap ROM MOTOROLA DSP56012 User’s Manual...
  • Page 232 ; Delay needed for Op. Mode change ; used to clear BCR register. (r0) ; Then go to destination address. ; This code fills the unused bootstrap ROM locations with their address dup $020-* dc * endm DSP56012 User’s Manual MOTOROLA...
  • Page 233 APPENDIX B PROGRAMMING REFERENCE MOTOROLA DSP56012 User’s Manual...

  • Page 234: B.1 Introduction

    Control Register ....... B-32 Status Registers ....... B-32 DSP56012 User’s Manual MOTOROLA...

  • Page 235: Introduction

    Table B-3 on page B-8 summarizes the instruction set. For more complete and detailed information about the instructions, consult the DSP56000 Family Manual . PROGRAMMING SHEETS Pages B-15 through B-32 are programming sheets for each of the complete set of programmable registers on the DSP. MOTOROLA DSP56012 User’s Manual...

  • Page 236: Figure B-1 On-Chip Peripheral Memory Map

    = Unused and reserved; read as a random number; should not be written, to ensure future compatibility = Unused and reserved; consult the appropriate chapter for information on how to ensure future compatibility Figure B-1 On-chip Peripheral Memory Map DSP56012 User’s Manual MOTOROLA...

  • Page 237: Table B-1 Interrupt Starting Addresses And Sources

    0–2 SAI Right Channel Transmitter if TXIL = 1 P: $0044 0–2 SAI Transmitter Exception if TXIL = 1 P: $0046 0–2 SAI Left Channel Receiver if RXIL = 1 P: $0048 0–2 SAI Right Channel Receiver if RXIL = 1 MOTOROLA DSP56012 User’s Manual...
  • Page 238 0–2 DAX Transmit Register Empty P: $0058 Available for Host Command P: $007E Available for Host Command Table B-2 Interrupt Priorities Within an IPL Priority Interrupt Level 3 (Nonmaskable) Highest Hardware RESET Illegal Instruction Stack Error Trace Lowest DSP56012 User’s Manual MOTOROLA...
  • Page 239 SHI Transmit Underrun Error SHI Receive FIFO Full SHI Transmit Data SHI Receive FIFO Not Empty HI Command Interrupt HI Receive Data Interrupt HI Transmit Data Interrupt DAX Transmit Underrun Error DAX Block Transferred Lowest DAX Transmit Register Empty MOTOROLA DSP56012 User’s Manual...
  • Page 240 * indicates that the bit may be set according to the definition, depending on parallel move conditions ? indicates that the bit is set according to a special definition; see the instruction descriptions in Appendix A of the DSP56000 Family Manual (DSP56KFAMUM/AD) 0 indicates that the bit is cleared DSP56012 User’s Manual MOTOROLA...
  • Page 241 * indicates that the bit may be set according to the definition, depending on parallel move conditions ? indicates that the bit is set according to a special definition; see the instruction descriptions in Appendix A of the DSP56000 Family Manual (DSP56KFAMUM/AD) 0 indicates that the bit is cleared MOTOROLA DSP56012 User’s Manual...
  • Page 242 * indicates that the bit may be set according to the definition, depending on parallel move conditions ? indicates that the bit is set according to a special definition; see the instruction descriptions in Appendix A of the DSP56000 Family Manual (DSP56KFAMUM/AD) 0 indicates that the bit is cleared B-10 DSP56012 User’s Manual MOTOROLA...
  • Page 243 * indicates that the bit may be set according to the definition, depending on parallel move conditions ? indicates that the bit is set according to a special definition; see the instruction descriptions in Appendix A of the DSP56000 Family Manual (DSP56KFAMUM/AD) 0 indicates that the bit is cleared MOTOROLA DSP56012 User’s Manual B-11...
  • Page 244 * indicates that the bit may be set according to the definition, depending on parallel move conditions ? indicates that the bit is set according to a special definition; see the instruction descriptions in Appendix A of the DSP56000 Family Manual (DSP56KFAMUM/AD) 0 indicates that the bit is cleared B-12 DSP56012 User’s Manual MOTOROLA...
  • Page 245 * indicates that the bit may be set according to the definition, depending on parallel move conditions ? indicates that the bit is set according to a special definition; see the instruction descriptions in Appendix A of the DSP56000 Family Manual (DSP56KFAMUM/AD) 0 indicates that the bit is cleared MOTOROLA DSP56012 User’s Manual B-13...
  • Page 246 * indicates that the bit may be set according to the definition, depending on parallel move conditions ? indicates that the bit is set according to a special definition; see the instruction descriptions in Appendix A of the DSP56000 Family Manual (DSP56KFAMUM/AD) 0 indicates that the bit is cleared B-14 DSP56012 User’s Manual MOTOROLA...
  • Page 247 Read/Write Reset = $0300 Mode Register (MR) Condition Code Register (CCR) = Reserved, write as 0 Status Register (SR) Note: The operation and function of the Status Register is detailed in the DSP56000 Family Manual MOTOROLA DSP56012 User’s Manual B-15...
  • Page 248 Programming Reference Date: Application: Programmer: Sheet 2 of 4 B-16 DSP56012 User’s Manual MOTOROLA...
  • Page 249 Programming Reference Date: Application: Programmer: Sheet 3 of 4 MOTOROLA DSP56012 User’s Manual B-17...
  • Page 250 Programming Reference Date: Application: Programmer: Sheet 4 of 4 B-18 DSP56012 User’s Manual MOTOROLA...
  • Page 251 0 = disable/1 = enable — interrupt on HCP Host Flags (HF3, HF2) general purpose read/write flags • • • HCIE HTIE HRIE Host Control Register (HCR) X:$FFE8 Read/Write Reset = $00 * = Reserved, write as 0 Host Control Register (HCR) MOTOROLA DSP56012 User’s Manual B-19...
  • Page 252 Host Receive Data Register (HORX) Host Transmit Data Register (HOTX) X:$FFEB Write Only Host Transmit Data (Usually Loaded by Program) Reset = $000000 Receive High Byte Receive Middle Byte Receive Low Byte Host Transmit Data Register (HOTX) B-20 DSP56012 User’s Manual MOTOROLA...
  • Page 253 Host Vector (HV[5:0]) Executive Interrupt Routine 0-63 Host Command (HC) 0 = Idle/1 = Interrupt DSP Command Vector Register (CVR) $1 Read/Write Reset = $17 * = Reserved, write as 0 Command Vector Register (CVR) MOTOROLA DSP56012 User’s Manual B-21...
  • Page 254 * = Reserved, write as 0 Interrupt Status Register (ISR) Interrupt Vector Number For Use By MC68000 Processor Family Vectored Interrupts. Interrupt Vector Register (IVR) $3 Read/Write Reset = $0F * = Reserved, write as 0 Interrupt Vector Register (IVR) B-22 DSP56012 User’s Manual MOTOROLA...
  • Page 255 Programming Reference Date: Application: Programmer: Sheet 5 of 5 MOTOROLA DSP56012 User’s Manual B-23...
  • Page 256 Programming Reference Date: Application: Programmer: Sheet 1 of 3 B-24 DSP56012 User’s Manual MOTOROLA...
  • Page 257 Programming Reference Date: Application: Programmer: Sheet 2 of 3 MOTOROLA DSP56012 User’s Manual B-25...
  • Page 258 Programming Reference Date: Application: Programmer: Sheet 3 of 3 B-26 DSP56012 User’s Manual MOTOROLA...
  • Page 259 15 14 13 12 11 10 RRDF RLDF RXIL RXIE RDWT RREL RCKP RLRS RDIR RWL1 RWL0 RMST R1EN R0EN Receiver Control/Status Register (RCS) X:$FFE1 Reset = $0000 SAI Receiver Control/Status Register (RCS) = Reserved, write as 0 MOTOROLA DSP56012 User’s Manual B-27...
  • Page 260 15 14 13 12 11 10 Transmitter Control/ TRDE TLDE TXIL TXIE TDWE TREL TCKP TLRS TDIR TWL1 TWL0 TMST T2EN T1EN T0EN Status Register (TCS) X:$FFE4 Reset = $0000 SAI Transmitter Control/Status Register (TCS) = Reserved, write as 0 B-28 DSP56012 User’s Manual MOTOROLA...
  • Page 261 Programming Reference Date: Application: Programmer: Sheet 3 of 4 MOTOROLA DSP56012 User’s Manual B-29...
  • Page 262 Programming Reference Date: Application: Programmer: Sheet 4 of 4 B-30 DSP56012 User’s Manual MOTOROLA...
  • Page 263 Programming Reference Date: Application: Programmer: Sheet 1 of 1 MOTOROLA DSP56012 User’s Manual B-31...
  • Page 264 Programming Reference Date: Application: Programmer: Sheet 1 of 1 B-32 DSP56012 User’s Manual MOTOROLA...
  • Page 265 General Purpose I/O — See Section 7 DAX Block transfer (XBLK) flag 8-11 General Purpose I/O (GPIO) 1-19 DAX Channel A Channel status (XCA) bit 8-9 General Purpose Input/Output (GPIO) 1-10 DAX Channel A User data (XUA) bit 8-9 GPIO Motorola...
  • Page 266 Host Flag 2 bit (HF2) 4-31 usage considerations—DSP side 4-21 Host Flag 3 bit (HF3) 4-31 HI Command Interrupt Enable (HCIE) bit 4-15 Host Flag operation 4-16 HI Command Pending (HCP) bit 4-17 Host Interface 2-10 HI DMA bit 4-21 Host Interface (HI) 4-9 Motorola...
  • Page 267 Transmit Data In Slave Mode 5-27 bit 4—Host Flag 3 bit (HF3) 4-31 C Bus Acknowledgment 5-21 bit 5—reserved 4-31 C Mode 5-3 bit 6—DMA Status bit (DMA) 4-32 S Format 1-19 bit 7—Host Request bit (HOREQ) 4-32 I2S Format 6-3 IVR register 4-32 Motorola...
  • Page 268 Reserved Bits 6-10 Programming Model Initiating A Transmit Session 6-24 GPIO 7-3 Internal Architecture 6-4 SAI 6-8 Internal Interrupt Priorities 6-9 SHI—DSP Side 5-6 Operation During Stop 6-24 SHI—Host Side 5-5 Operation Under Irregular Conditions 6-25 programming model Programming Considerations 6-24 Motorola...
  • Page 269 Transmit Section 6-6 Programming Model—DSP Side 5-6 Transmit Section Block Diagram 6-7 Programming Model—Host Side 5-5 Transmitter Clock Polarity Programming 6-20 Slave Address Register—DSP Side 5-9 Transmitter Control/Status Register SHI Noise Reduction Filter Mode 5-12 (TCS) 6-17 SPI 1-18 5-19 Motorola...
  • Page 270 TX0, TX1 and TX2 (SAI Transmit Data Registers) 6-23 TXDE bit 4-31 TXH register 4-33 TXIE (TCS Transmitter Interrupt Enable) 6-21 TXIL (TCS Transmitter Interrupt Location) 6-22 TXL register 4-33 TXM register 4-33 X Data Memory 1-15 Y Data Memory 1-15 Motorola...

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