Figure 7-15 Essi Pin Configuration For Clocks, Frame Syncs, And Flags; Serial Output Flag 1 (Of1) Crb Bit 1; Serial Control Direction 0 (Scd0) Crb Bit 2 - Motorola DSP56305 User Manual

7.4.2.1.2

Serial Output Flag 1 (OF1) CRB Bit 1

When the ESSI is in Synchronous mode and transmitter 2 is disabled (TE2 = 0), the SC1
signal is configured as ESSI flag 1. If the serial control direction bit (SCD1) is set, the SC1
signal is an output. Data present in bit OF1 is written to SC1 at the beginning of the
frame in Normal mode or at the beginning of the next time slot in Network mode.
Bit OF1 is cleared by a hardware reset signal or by a software reset instruction.
7.4.2.2

Serial Control Direction 0 (SCD0) CRB Bit 2

In Synchronous mode (SYN = 1) when transmitter 1 is disabled (TE1 = 0), or in
Asynchronous mode (SYN = 0), SCD0 controls the direction of the SC0 I/O signal. When
SCD0 is set, SC0 is an output; when SCD0 is cleared, SC0 is an input.
When TE1 is set, the value of SCD0 is ignored and the SC0 signal is always an output.
Bit SCD0 is cleared by a hardware reset signal or by a software reset instruction.
Bit Value
Bit Number

Figure 7-15 ESSI Pin Configuration for Clocks, Frame Syncs, and Flags

MOTOROLA
Enhanced Synchronous Serial Interface (ESSI)
0 = Input
Synchronous Mode (SYN = 1)
Tx/Rx
Clock F.S.
5 4
SCKD SCD2
CRB
Pin SCKn SCn2
Clock F.S.
Tx
Asynchronous Mode (SYN = 0)
DSP56305 User's Manual
ESSI Programming Model
1 = Output
Flag 1 Flag 0
3 2
SCD1 SCD0
SCn1 SCn0
F.S. Clock
Rx
AA0849
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