Motorola DSP56303 Manuals

Manuals and User Guides for Motorola DSP56303. We have 1 Motorola DSP56303 manual available for free PDF download: User Manual

Motorola DSP56303 User Manual

Motorola DSP56303 User Manual (320 pages)

24-Bit Digital Signal Processor

Brand: Motorola | Category: Signal Processors | Size: 4.26 MB

Table of Contents

Table of Contents
5
Chapter 1 Overview

17
- Manual Organization
  17
- Manual Conventions
  18
  - High True/Low True Signal Conventions
    18
- Features
  20
- DSP56300 Core
  20
- DSP56300 Core Functional Blocks
  21
- Data ALU
  22
- 1.5.1.1 Data ALU Registers
  22
- Multiplier-Accumulator (MAC)
  22
- Address Generation Unit (AGU)
  23
- Program Control Unit (PCU)
  23
- PLL and Clock Oscillator
  24
- JTAG TAP and Once Module
  25
- On-Chip Memory
  25
- Off-Chip Memory Expansion
  26
- Internal Buses
  26
- Dma
  27
  - DSP56303 Block Diagram
    27
- Peripherals
  28
- GPIO Functionality
  28
- Hi08
  28
- Essi
  29
- Sci
  29
- Timer Module
  30
Chapter 2 Signals/Connections

31
- DSP56303 Functional Signal Groupings
  31
- Signals Identified by Functional Group
  32
- Grounds
  32
- Power
  33
  - Power Inputs
    33
- Ground
  34
- Clock
  35
- Phase Lock Loop (PLL)
  35
  - Clock Signals
    35
  - Phase Lock Loop Signals
    35
- External Memory Expansion Port (Port A)
  36
- External Address Bus
  36
- External Data Bus
  36
- External Bus Control
  36
- Interrupt and Mode Control
  39
- Host Interface (HI08)
  40
- Host Port Usage Considerations
  40
- Host Port Configuration
  41
- Enhanced Synchronous Serial Interface 0 (ESSI0)
  45
- Enhanced Synchronous Serial Interface 1 (ESSI1)
  47
- Serial Communication Interface (SCI)
  49
- Timers
  50
  - Triple Timer Signals
    50
- Jtag/Once Interface
  51
Chapter 3 Memory Configuration

53
Chapter 4 Core Configuration

67
Chapter 5 Programming the Peripherals

105
- Peripheral Initialization Steps
  105
- Mapping the Control Registers
  106
- Reading Status Registers
  106
  - Memory Mapping of Peripherals Control Registers
    106
- Data Transfer Methods
  107
- Polling
  107
- Interrupts
  107
- Dma
  109
  - DMA-Accessible Registers
    109
- Advantages and Disadvantages
  110
- General-Purpose Input/Output (GPIO)
  110
- Port B Signals and Registers
  111
  - Port B Signals
    111
- Port C Signals and Registers
  112
- Port D Signals and Registers
  112
  - Port C Signals
    112
  - Port D Signals
    112
- Port E Signals and Registers
  113
- Triple Timer Signals and Registers
  113
  - Port E Signals
    113
  - Triple Timer Signals
    113
Chapter 6 Host Interface (HI08)

115
- Features
  115
- DSP Core Interface
  115
- Host Processor Interface
  116
- Host Port Signals
  117
  - HI08 Signal Definitions for Operational Modes
    117
- Overview
  118
  - HI08 Data Strobe Signals
    118
  - HI08 Host Request Signals
    118
  - HI08 Block Diagram
    119
- Operation
  120
- Software Polling
  121
- Core Interrupts and Host Commands
  121
  - HI08 Core Interrupt Operation
    122
- Core DMA Access
  123
- Host Requests
  123
- Endian Modes
  125
  - HI08 Read and Write Operations in Little Endian Mode
    125
- Boot-Up Using the HI08 Host Port
  126
  - HI08 Read and Write Operations in Big Endian Mode
    126
  - HI08 Boot Modes
    126
- DSP Core Programming Model
  127
- Host Control Register (HCR)
  127
  - Command Vector Register (CVR)
    128
  - Host Control Register (HCR) Bit Definitions
    128
- Host Status Register (HSR)
  129
  - Host Status Register (HSR) Bit Definitions
    129
- Host Data Direction Register (HDDR)
  130
- Host Data Register (HDR)
  130
- Host Base Address Register (HBAR)
  131
- Host Port Control Register (HPCR)
  132
  - Host Port Control Register (HPCR) Bit Definitions
    132
- Host Transmit (HTX) Register
  135
  - Single-Strobe Mode
    135
  - Dual-Strobe Mode
    135
- Host Receive (HRX) Register
  136
- DSP-Side Registers after Reset
  136
- Host Programmer Model
  137
- Interface Control Register (ICR)
  138
  - Host-Side Register Map
    138
  - Interface Control Register (ICR) Bit Definitions
    139
- Command Vector Register (CVR)
  140
- Interface Status Register (ISR)
  141
  - Command Vector Register (CVR) Bit Definitions
    141
  - Interface Status Register (ISR) Bit Definitions
    142
- Interrupt Vector Register (IVR)
  143
- Receive Data Registers (RXH:RXM:RXL)
  144
- Transmit Data Registers (TXH:TXM:TXL)
  144
- Host-Side Registers after Reset
  145
- Programming Model Quick Reference
  146
  - HI08 Programming Model, DSP Side
    146
  - HI08 Programming Model: Host Side
    148
Chapter 7 Enhanced Synchronous Serial Interface (ESSI)

149
- ESSI Block Diagram
  149
- ESSI Enhancements
  150
- ESSI Data and Control Signals
  151
- Serial Transmit Data Signal (STD)
  151
- Serial Receive Data Signal (SRD)
  151
- Serial Clock (SCK)
  151
  - ESSI Clock Sources
    151
- Serial Control Signal (SC0)
  152
- Serial Control Signal (SC1)
  152
  - Mode and Signal Definitions
    153
- Serial Control Signal (SC2)
  154
- Operation
  154
- ESSI after Reset
  154
- Initialization
  154
- Exceptions
  155
- Operating Modes: Normal, Network, and On-Demand
  158
- Normal/Network/On-Demand Mode Selection
  158
- Synchronous/Asynchronous Operating Modes
  159
- Frame Sync Selection
  159
- Frame Sync Signal Format
  159
- Frame Sync Length for Multiple Devices
  160
- Word Length Frame Sync and Data Word Timing
  160
- Frame Sync Polarity
  160
- Byte Format (LSB/MSB) for the Transmitter
  161
- Flags
  161
- ESSI Programming Model
  162
- ESSI Control Register a (CRA)
  162
- ESSI Control Register B (CRB)
  166
- ESSI Status Register (SSISR)
  176
  - ESSI Status Register (SSISR) Bit Definitions
    176
- ESSI Receive Shift Register
  177
- ESSI Receive Data Register (RX)
  178
- ESSI Transmit Shift Registers
  178
  - ESSI Data Path Programming Model (SHFD = 0)
    179
  - ESSI Data Path Programming Model (SHFD = 1)
    180
- ESSI Transmit Data Registers (TX[2-0])
  181
- ESSI Time Slot Register (TSR)
  181
- Transmit Slot Mask Registers (TSMA, TSMB)
  181
  - ESSI Transmit Slot Mask Register a (TSMA)
    181
  - ESSI Transmit Slot Mask Register B (TSMB)
    182
- Receive Slot Mask Registers (RSMA, RSMB)
  183
  - ESSI Receive Slot Mask Register a (RSMA)
    183
  - ESSI Receive Slot Mask Register B (RSMB)
    183
- GPIO Signals and Registers
  184
- Port Control Registers (PCRC and PCRD)
  184
  - Port Control Registers (PCRC X:$FFFFBF) (PCRD X:$FFFAF)
    184
- Port Direction Registers (PRRC and PRRD)
  185
  - Port Direction Registers (PRRC X:$FFFFBE) (PRRD X: $FFFFAE)
    185
  - ESSI Port Signal Configurations
    185
- Port Data Registers (PDRC and PDRD)
  186
  - Port Data Registers (PDRC X:$FFFFBD) (PDRD X: $FFFFAD)
    186
Chapter 8 Serial Communication Interface (SCI)

187
- Operating Modes
  187
- Synchronous Mode
  188
- Asynchronous Mode
  188
- Multidrop Mode
  188
- 8.1.3.1 Transmitting Data and Address Characters
  189
- 8.1.3.2 Wired-OR Mode
  189
- 8.1.3.3 Idle Line Wakeup
  189
- 8.1.3.4 Address Mode Wakeup
  189
- I/O Signals
  189
- Receive Data (RXD)
  190
- Transmit Data (TXD)
  190
- SCI Serial Clock (SCLK)
  190
- SCI after Reset
  191
  - SCI Registers after Reset
    191
- SCI Initialization
  192
- Preamble, Break, and Data Transmission Priority
  193
- Bootstrap Loading through the SCI (Boot Mode 2 or A)
  194
- Exceptions
  194
- SCI Programming Model
  195
  - SCI Control Register (SCR
    195
  - SCI Status Register
    195
  - SCI Data Word Formats (SSFTD = 1), 1
    196
  - SCI Data Word Formats (SSFTD = 0), 2
    197
- SCI Control Register (SCR)
  198
  - SCI Control Register (SCR) Bit Definitions
    198
- SCI Status Register (SSR)
  203
  - SCI Status Register (SSR) Bit Definitions
    203
- SCI Clock Control Register (SCCR)
  205
  - SCI Clock Control Register (SCCR) Bit Definitions
    205
  - SCI Baud Rate Generator
    206
  - X Serial Clock
    207
- SCI Data Registers
  208
- SCI Receive Register (SRX)
  208
  - SCI Programming Model-Data Registers
    208
- SCI Transmit Register (STX)
  209
- GPIO Signals and Registers
  210
- Port E Control Register (PCRE)
  210
- Port E Direction Register (PRRE)
  211
- Port E Data Register (PDRE)
  211
  - Port Data Registers (PDRE X:$FFFF9D)
    211
Chapter 9 Triple Timer Module

213
- Overview
  213
- Triple Timer Module Block Diagram
  214
- Individual Timer Block Diagram
  214
- Operation
  215
- Timer after Reset
  215
  - Timer Module Block Diagram
    215
- Timer Initialization
  216
- Timer Exceptions
  216
- Operating Modes
  217
- Triple Timer Modes
  218
- Timer GPIO (Mode 0)
  218
  - Timer Mode (TRM = 1)
    219
  - Timer Mode (TRM = 0)
    219
- Timer Pulse (Mode 1)
  220
  - Pulse Mode (TRM = 1)
    220
  - Pulse Mode (TRM = 0)
    221
- Timer Toggle (Mode 2)
  222
  - Toggle Mode, TRM = 1
    222
  - Toggle Mode, TRM = 0
    223
- Timer Event Counter (Mode 3)
  224
  - Event Counter Mode, TRM = 1
    224
  - Event Counter Mode, TRM = 0
    225
- Signal Measurement Modes
  226
- Measurement Input Width (Mode 4)
  226
- Measurement Input Period (Mode 5)
  226
- Measurement Capture (Mode 6)
  226
- Pulse Width Modulation (PWM, Mode 7)
  231
  - Pulse Width Modulation Toggle Mode, TRM = 1
    232
  - Pulse Width Modulation Toggle Mode, TRM = 0
    233
- Watchdog Modes
  234
- Watchdog Pulse (Mode 9)
  234
  - Watchdog Pulse Mode
    235
- Watchdog Toggle (Mode 10)
  236
- 9.3.4.3 Reserved Modes
  237
- Special Cases
  237
- DMA Trigger
  237
- Triple Timer Module Programming Model
  237
- Prescaler Counter
  237
  - Timer Module Programmer's Model
    238
- Timer Prescaler Load Register (TPLR)
  239
  - Timer Prescaler Load Register (TPLR) Bit Definitions
    239
- Timer Prescaler Count Register (TPCR)
  240
- Timer Control/Status Register (TCSR)
  240
- Timer Load Register (TLR)
  245
- Timer Compare Register (TCPR)
  246
- Timer Count Register (TCR)
  246
Bootstrap Program

247

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