Motorola Digital DNA MSC8101 Technical Data Manual
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Motorola Digital DNA MSC8101 Technical Data Manual

Motorola Digital DNA MSC8101 Technical Data Manual

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Technical Data
Advance Information
MSC8101/D
Rev. 6, 11/2002
Networking Digital
Signal Processor
(mask set 2K42A)
Interface
TDMs
The Motorola
MSC8101 16-bit
Digital Signal
Processor (DSP) is the
Peripherals
first member of the
family of DSPs based
on the StarCore™
SC140 DSP core. The
MSC8101 is offered in
three core speed levels:
250, 275, and 300 MHz.
The Motorola MSC8101 DSP is a very versatile
device that integrates the high-performance SC140
four-ALU (Arithmetic Logic Unit) DSP core along
with 512 KB of on-chip memory, a
Communications Processor Module (CPM), a
64-bit bus, a very flexible System Integration Unit
(SIU), and a 16-channel DMA engine on a single
device. With its four-ALU core, the MSC8101 can
execute up to four multiply-accumulate (MAC)
operations in a single clock cycle. The MSC8101
CPM is a 32-bit RISC-based communications
protocol engine that can network to Time-Division
Multiplexed (TDM) highways, Ethernet, and
CPM
3 × FCC
UTOPIA
2 × MCC
MII
4 × SCC
•
{
2 × SMC
•
•
SPI
I2C
Other
Extended Core
Address
Program
Register
Sequencer
File
Address
SC140
ALU
Core
JTAG
EOnCE™
Power
Management
Figure 1. MSC8101 Block Diagram
捷多邦，专业PCB打样工厂，24小时加急出货
SIU
64-bit System Bus
Interrupt
Controller
Timers
Parallel I/O
DMA
Baud Rate
Generators
Engine
Dual Ported
RAM
Bridge
2 × SDMA
RISC
64-bit Local Bus
128-bit QBus
Q2PPC
Bridge
Data ALU
Register
Boot
File
ROM
Data
SRAM
ALU
512 KB
Clock/PLL
Asynchronous Transfer mode (ATM) backbones.
The MSC8101 60x-compatible bus interface
facilitates its connection to multi-master system
architectures. The very large on-chip memory, 512
KB, reduces the need for off-chip program and
data memories. The MSC8101 offers 1500 DSP
MMACS (1200 core and 300 EFCOP) or 3600
RISC MIPS performance using an internal 300
MHz clock with a 1.6 V core and independent
3.3 V input/output (I/O). MSC8101 power
dissipation is estimated at less than 0.6 W. Figure
1 shows a block diagram of the MSC8101
processor.
MEMC
64/32-bit
System
PIT
Bus
System Protection
Reset Control
Clock Control
SIC_EXT
Interrupts
SIC
MEMC
PIC
Interrupts
EFCOP
8/16-bit
Host
HDI16
Interface
L1 Interface
128-bit P-Bus
64-bit XA Data Bus
64-bit XB Data Bus

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Summary of Contents for Motorola Digital DNA MSC8101

  • Page 1 64-bit XA Data Bus Management 64-bit XB Data Bus Figure 1. MSC8101 Block Diagram The Motorola MSC8101 DSP is a very versatile Asynchronous Transfer mode (ATM) backbones. device that integrates the high-performance SC140 The MSC8101 60x-compatible bus interface four-ALU (Arithmetic Logic Unit) DSP core along...

  • Page 2: Table Of Contents

    Table of Contents MSC8101 Features............................. iii Target Applications ............................iv Product Documentation............................iv Chapter 1 Signal/ Connection Descriptions Signal Groupings.............................. 1-1 Power Signals..............................1-4 Clock Signals ..............................1-5 Reset, Configuration, and EOnCE Event Signals .................... 1-6 System Bus, HDI16, and Interrupt Signals ...................... 1-8 Memory Controller Signals..........................

  • Page 3: Msc8101 Features

    MSC8101 Features • SC140 Core — Architecture optimized for efficient C/C++ code compilation — Four 16-bit ALUs and two 32-bit AGUs — 1200 DSP MIPS, 1200 MMACS, 3000 RISC MIPS, running at 300 MHz — Very low power dissipation—less than 0.25 W for the core running full speed at 1.6 V —...

  • Page 4: Target Applications

    Documentation is available from the following sources (see back cover for detailed information): • A local Motorola distributor • A Motorola semiconductor sales office • A Motorola Literature Distribution Center • The World Wide Web (WWW) Table 1.

  • Page 5: Signal Groupings

    Chapter 1 Signal/ Connection Descriptions 1.1 Signal Groupings The MSC8101 external signals are organized into functional groups, as shown in Table 1-1, Figure 1-1, and Figure 1-2. Table 1-1 lists the functional groups, the number of signal connections in each group, and references the table that gives a detailed listing of multiplexed signals within each group.
  • Page 6 Signal Groupings ↔ A[0–31] ↔ TT[0–4] → 14 ↔ TSIZ[0–3] → 25 VDDH ↔ TBST → VCCSYN ↔ IRQ1 → VCCSYN1 → Reserved BADDR[29–31] IRQ[2–3, 5] ↔ BR → 37 ↔ BG → GNDSYN ↔ ABB → GNDSYN1 IRQ2 ↔ TS ↔...
  • Page 7 Signal Groupings FCC1 ATM/UTOPIA FCC1 MPHY MPHY Master HDLC/ Master Ethernet HDLC mux poll transp. dir. poll or Slave Serial Nibble GPIO TXENB PA31 TXCLAV TXCLAV0 PA30 TXSOC TX_ER PA29 RXENB TX_EN PA28 RXSOC RX_DV PA27 RXCLAV RXCLAV0 RX_ER SDMA PA26 TXD0 MSNUM0...

  • Page 8: Power Signals

    Power Signals 1.2 Power Signals Table 1-1. Power and Ground Signal Inputs Power Name Description Internal Logic Power dedicated for use with the device core. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the V power rail.

  • Page 9: Clock Signals

    Clock Signals 1.3 Clock Signals Table 1-2. Clock Signals Signal Type Signal Description Name CLKIN Input Clock In Primary clock input to the MSC8101 PLL. MODCK1 Input Clock Mode Input 1 Defines the operating mode of internal clock circuits. Output Transfer Code 0 Supplies information that can be useful for debugging bus transactions initiated by the MSC8101.

  • Page 10: Reset, Configuration, And Eonce Event Signals

    Reset, Configuration, and EOnCE Event Signals 1.4 Reset, Configuration, and EOnCE Event Signals Table 1-3. Reset, Configuration, and EOnCE Event Signals Signal Name Type Signal Description DBREQ Input Debug Request Determines whether to go into SC140 Debug mode when PORESET is deasserted. Enhanced OnCE (EOnCE) Event 0 After PORESET is deasserted, you can configure EE0 as an input (default) or an output.
  • Page 11 Reset, Configuration, and EOnCE Event Signals Table 1-3. Reset, Configuration, and EOnCE Event Signals (Continued) Signal Name Type Signal Description BTM[0–1] Input Boot Mode 0–1 Determines the MSC8101 boot mode when PORESET is deasserted. See the Emulation and Debug chapter in the SC140 DSP Core Reference Manual for details on how to set these pins.

  • Page 12: System Bus, Hdi16, And Interrupt Signals

    System Bus, HDI16, and Interrupt Signals 1.5 System Bus, HDI16, and Interrupt Signals The system bus, HDI16, and interrupt signals are grouped together because they use a common set of signal lines. Individual assignment of a signal to a specific signal line is configured through registers in the System Interface Unit (SIU) and the Host Interface (HDI16).
  • Page 13 System Bus, HDI16, and Interrupt Signals Table 1-4. System Bus, HDI16, and Interrupt Signals (Continued) Signal Data Flow Description Reserved Output The primary configuration is reserved. BADDR29 Output Burst Address 29 One of five outputs of the memory controller. These pins connect directly to memory devices controlled by the MSC8101 memory controller.
  • Page 14 System Bus, HDI16, and Interrupt Signals Table 1-4. System Bus, HDI16, and Interrupt Signals (Continued) Signal Data Flow Description Input/Output Bus Transfer Start Signals the beginning of a new address bus tenure. The MSC8101 asserts this signal when one of its internal bus masters (SC140 core or DMA) begins an address tenure.
  • Page 15 System Bus, HDI16, and Interrupt Signals Table 1-4. System Bus, HDI16, and Interrupt Signals (Continued) Signal Data Flow Description Input/Output Data Bus Bit 52 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. HCS1 Input Host Chip Select...
  • Page 16 System Bus, HDI16, and Interrupt Signals Table 1-4. System Bus, HDI16, and Interrupt Signals (Continued) Signal Data Flow Description Input/Output Data Bus Bit 56 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. HACK/HACK Output Host Acknowledge...
  • Page 17 System Bus, HDI16, and Interrupt Signals Table 1-4. System Bus, HDI16, and Interrupt Signals (Continued) Signal Data Flow Description Reserved Input The primary configuration is reserved. Input/Output Data Parity 0 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity zero pin should give odd parity (odd number of ones) on the group of signals that includes data parity 0 and D[0–7].
  • Page 18 System Bus, HDI16, and Interrupt Signals Table 1-4. System Bus, HDI16, and Interrupt Signals (Continued) Signal Data Flow Description IRQ4 Input Interrupt Request 4 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Input/Output Data Parity 4 The agent that drives the data bus also drives the data parity signals.
  • Page 19 System Bus, HDI16, and Interrupt Signals Table 1-4. System Bus, HDI16, and Interrupt Signals (Continued) Signal Data Flow Description Input/Output Transfer Error Acknowledge Indicates a bus error. masters within the MSC8101 monitor the state of this pin. The MSC8101 internal bus monitor can assert this pin if it identifies a bus transfer that is hung.

  • Page 20: Memory Controller Signals

    Memory Controller Signals 1.6 Memory Controller Signals Refer to the Memory Controller chapter in the MSC8101 Reference Manual (MSC8101RM/D) for detailed information about configuring these signals. Table 1-2. Memory Controller Signals Data Signal Description Flow CS[0–7] Output Chip Select Enable specific memory devices or peripherals connected to MSC8101 buses. BCTL1 Output Buffer Control 1...
  • Page 21 Memory Controller Signals Table 1-2. Memory Controller Signals (Continued) Data Signal Description Flow Output Bus Output Enable Output of the bus GPCM. Controls the output buffer of memory devices during read operations. PSDRAS Output Bus SDRAM RAS Output from the bus SDRAM controller. This pin should connect to the SDRAM Row Address Strobe (RAS) input signal.

  • Page 22: Communications Processor Module (Cpm) Ports

    Communications Processor Module (CPM) Ports 1.7 Communications Processor Module (CPM) Ports The MSC8101 CPM supports a subset of signals included in the MPC8260. The following sections describe the functionality of the signals in the MSC8101. • The MSC8101 CPM includes the following set of communication controllers: •...
  • Page 23 Communications Processor Module (CPM) Ports 1.7.1 Port A Signals Table 1-3. Port A Signals Name Dedicated General- Peripheral Controller: I/O Data Description Purpose Dedicated Signal Direction Protocol PA31 FCC1: TXENB Output FCC1: UTOPIA Master Transmit Enable UTOPIA master In the ATM UTOPIA interface supported by FCC1, TXENB is asserted by the MSC8101 (UTOPIA master PHY) when there is valid transmit cell data (TXD[0–7]).
  • Page 24 Communications Processor Module (CPM) Ports Table 1-3. Port A Signals (Continued) Name Dedicated General- Peripheral Controller: I/O Data Description Purpose Dedicated Signal Direction Protocol PA29 FCC1: TXSOC Output FCC1: UTOPIA Transmit Start of Cell UTOPIA master In the ATM UTOPIA interface supported by FCC1. TXSOC is asserted by the MSC8101 (UTOPIA master PHY) when TXD[0–7] contains the first valid byte of the cell.
  • Page 25 Communications Processor Module (CPM) Ports Table 1-3. Port A Signals (Continued) Name Dedicated General- Peripheral Controller: I/O Data Description Purpose Dedicated Signal Direction Protocol PA26 FCC1: RXCLAV Output FCC1: UTOPIA Slave Receive Cell Available UTOPIA slave In the ATM UTOPIA interface supported by FCC1. RXCLAV is asserted by the MSC8101 (UTOPIA slave PHY) when one complete ATM cell is available for transfer.
  • Page 26 Communications Processor Module (CPM) Ports Table 1-3. Port A Signals (Continued) Name Dedicated General- Peripheral Controller: I/O Data Description Purpose Dedicated Signal Direction Protocol PA22 FCC1: TXD3 Output FCC1: UTOPIA Transmit Data Bit 3 UTOPIA TXD[0–7] is part of the ATM UTOPIA interface supported by FCC1.
  • Page 27 Communications Processor Module (CPM) Ports Table 1-3. Port A Signals (Continued) Name Dedicated General- Peripheral Controller: I/O Data Description Purpose Dedicated Signal Direction Protocol PA18 FCC1: TXD7 Output FCC1: UTOPIA Transmit Data Bit 7. UTOPIA TXD[0–7] is part of the ATM UTOPIA interface supported by FCC1.
  • Page 28 Communications Processor Module (CPM) Ports Table 1-3. Port A Signals (Continued) Name Dedicated General- Peripheral Controller: I/O Data Description Purpose Dedicated Signal Direction Protocol PA15 FCC1: RXD5 Input FCC1: UTOPIA Receive Data Bit 5 UTOPIA In the ATM UTOPIA interface supported by FCC1. The MSC8101 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7].
  • Page 29 Communications Processor Module (CPM) Ports Table 1-3. Port A Signals (Continued) Name Dedicated General- Peripheral Controller: I/O Data Description Purpose Dedicated Signal Direction Protocol PA11 FCC1: RXD1 Input FCC1: UTOPIA RX Receive Data Bit 1 UTOPIA In the ATM UTOPIA interface supported by FCC1. The MSC8101 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7].
  • Page 30 Communications Processor Module (CPM) Ports Table 1-3. Port A Signals (Continued) Name Dedicated General- Peripheral Controller: I/O Data Description Purpose Dedicated Signal Direction Protocol SMC2: SMRXD Input SMC2: Serial Management Receive Data Supported by SMC2. The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock.
  • Page 31 Communications Processor Module (CPM) Ports 1.7.2 Port B Signals Table 1-4. Port B Signals Name Dedicated General- Peripheral Controller: I/O Data Description Purpose Dedicated I/O Direction Protocol PB31 FCC2: TX_ER Output FCC2: Media Independent Interface Transmit Error In the MII interface supported by FCC2. TX_ER is asserted by the MSC8101 to force propagation of transmit errors.
  • Page 32 Communications Processor Module (CPM) Ports Table 1-4. Port B Signals (Continued) Name Dedicated General- Peripheral Controller: I/O Data Description Purpose Dedicated I/O Direction Protocol PB28 FCC2: RTS Output FCC2: Request to Send HDLC serial , HDLC nibble , One of the standard modem interface signals supported by and transparent FCC2 (RTS, CTS, and CD).
  • Page 33 Communications Processor Module (CPM) Ports Table 1-4. Port B Signals (Continued) Name Dedicated General- Peripheral Controller: I/O Data Description Purpose Dedicated I/O Direction Protocol PB25 FCC2: TXD3 Output FCC2: MII and HDLC Nibble Transmit Data Bit 3 MII and HDLC nibble Supported by MII and HDLC nibble mode in FCC2.
  • Page 34 Communications Processor Module (CPM) Ports Table 1-4. Port B Signals (Continued) Name Dedicated General- Peripheral Controller: I/O Data Description Purpose Dedicated I/O Direction Protocol PB22 FCC2: TXD0 Output FCC2: MII and HDLC Nibble Transmit Data Bit 0 MII and HDLC nibble TXD[0–3] is supported by MII and HDLC nibble mode in FCC2.
  • Page 35 Communications Processor Module (CPM) Ports Table 1-4. Port B Signals (Continued) Name Dedicated General- Peripheral Controller: I/O Data Description Purpose Dedicated I/O Direction Protocol PB20 FCC2: RXD1 Input FCC2: MII and HDLC Nibble: Receive Data Bit 1 MII and HDLC nibble RXD[0–3] is supported by MII and HDLC nibble mode in FCC2.
  • Page 36 Communications Processor Module (CPM) Ports 1.7.3 Port C Signals Table 1-5. Port C Signals Name Dedicated General- Peripheral Controller: I/O Data Description Purpose Dedicated I/O Direction Protocol PC31 BRG1O Output Baud-Rate Generator 1 Output The CPM supports up to 8 BRGs. The BRGs can be used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins.
  • Page 37 Communications Processor Module (CPM) Ports Table 1-5. Port C Signals (Continued) Name Dedicated General- Peripheral Controller: I/O Data Description Purpose Dedicated I/O Direction Protocol PC29 BRG3O Output Baud-Rate Generator 3 Output The CPM supports up to 8 BRGs. The BRGs can be used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins.
  • Page 38 Communications Processor Module (CPM) Ports Table 1-5. Port C Signals (Continued) Name Dedicated General- Peripheral Controller: I/O Data Description Purpose Dedicated I/O Direction Protocol PC27 BRG5O Output Baud-Rate Generator 5 Output The CPM supports up to 8 BRGs. The BRGs can be used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins.
  • Page 39 Communications Processor Module (CPM) Ports Table 1-5. Port C Signals (Continued) Name Dedicated General- Peripheral Controller: I/O Data Description Purpose Dedicated I/O Direction Protocol PC25 BRG7O Output Baud-Rate Generator 7 Output The CPM supports up to 8 BRGs. The BRGs can be used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins.
  • Page 40 Communications Processor Module (CPM) Ports Table 1-5. Port C Signals (Continued) Name Dedicated General- Peripheral Controller: I/O Data Description Purpose Dedicated I/O Direction Protocol PC23 CLK9 Input Clock 9 The CPM supports up to 10 clock input pins. The clocks are sent to the bank-of-clocks selection logic, where they can be routed to the controllers.
  • Page 41 Communications Processor Module (CPM) Ports Table 1-5. Port C Signals (Continued) Name Dedicated General- Peripheral Controller: I/O Data Description Purpose Dedicated I/O Direction Protocol PC15 SMC2: SMTXD Output SMC2: Serial Management Transmit Data Supported by SMC2. The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock.
  • Page 42 Communications Processor Module (CPM) Ports Table 1-5. Port C Signals (Continued) Name Dedicated General- Peripheral Controller: I/O Data Description Purpose Dedicated I/O Direction Protocol PC13 SI1: L1ST4 Output Serial Interface 1: Layer 1 Strobe 4 In the time-slot assigner supported by SI1. The MSC8101 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis.
  • Page 43 Communications Processor Module (CPM) Ports Table 1-5. Port C Signals (Continued) Name Dedicated General- Peripheral Controller: I/O Data Description Purpose Dedicated I/O Direction Protocol SI2: L1ST1 Output Serial Interface 2: Strobe 1 In the time-slot assigner supported by SI2. The MSC8101 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis.
  • Page 44 Communications Processor Module (CPM) Ports Table 1-5. Port C Signals (Continued) Name Dedicated General- Peripheral Controller: I/O Data Description Purpose Dedicated I/O Direction Protocol SI2: L1ST2 Output Serial Interface 2: Layer 1 Strobe 2 In the time-slot assigner supported by SI2. The MSC8101 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis.
  • Page 45 Communications Processor Module (CPM) Ports Table 1-5. Port C Signals (Continued) Name Dedicated General- Peripheral Controller: I/O Data Description Purpose Dedicated I/O Direction Protocol SMC1: SMRXD Input SMC1: Receive Data Supported by SMC1. The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not all signals are used for all applications.
  • Page 46 Communications Processor Module (CPM) Ports 1.7.4 Port D Signals Table 1-6. Port D Signals Name Dedicated General- Peripheral Controller: I/O Data Description Purpose Dedicated I/O Direction Protocol PD31 SCC1: RXD Input SCC1: Receive Data Supported by SCC1. SCC1 receives serial data from RXD. DMA: DRACK1 Output DMA: Data Request Acknowledge 1...
  • Page 47 Communications Processor Module (CPM) Ports Table 1-6. Port D Signals (Continued) Name Dedicated General- Peripheral Controller: I/O Data Description Purpose Dedicated I/O Direction Protocol PD19 FCC1: TXADDR4 Output FCC1: Multi-PHY Master Transmit Address Bit 4 UTOPIA master Multiplexed Polling In the ATM UTOPIA master interface supported by FCC1 using multiplexed polling, this is transmit address bit 4.
  • Page 48 Communications Processor Module (CPM) Ports Table 1-6. Port D Signals (Continued) Name Dedicated General- Peripheral Controller: I/O Data Description Purpose Dedicated I/O Direction Protocol PD18 FCC1: RXADDR4 Output FCC1: UTOPIA Master Receive Address Bit 4 UTOPIA master In the ATM UTOPIA master interface supported by FCC1 using multiplexed polling, this is receive address bit 4.

  • Page 49: Jtag Test Access Port Signals

    JTAG Test Access Port Signals Table 1-6. Port D Signals (Continued) Name Dedicated General- Peripheral Controller: I/O Data Description Purpose Dedicated I/O Direction Protocol SMC1: SMSYN Input SMC1: Serial Management Synchronization Supported by SMC1. SMSYN is an input. The SMC interface consists of SMTXD, SMRXD, SMSYN and a clock.

  • Page 50: Reserved Signals

    Reserved Signals 1.9 Reserved Signals Table 1-8. Reserved Signals Signal Name Type Signal Description TEST Input Test Used for manufacturing testing. You must connect this input to GND. THERM[1–2] — Leave disconnected. SPARE1, 5 — Spare Pins Leave disconnected for backward compatibility with future revisions of this device. 1-46...

  • Page 51: Chapter 2 Specifications

    Chapter 2 Specifications 2.1 Introduction This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MSC8101 communications processor. For additional information, see the MSC8101 Reference Manual. Note: The MSC8101 electrical specifications are preliminary and many are from design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle.

  • Page 52: Recommended Operating Conditions

    Recommended Operating Conditions Table 2-1. Absolute Maximum Ratings (Continued) Rating Symbol Value Unit Notes: Functional operating conditions are given in Table 2-2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the listed limits may affect device reliability or cause permanent damage. The input voltage must not exceed the I/O supply V by more than 2.5 V at any time, including during power-on reset.

  • Page 53: Dc Electrical Characteristics

    DC Electrical Characteristics See Section 4.1, Thermal Design Considerations, on page 4-1 for details on these characteristics. 2.5 DC Electrical Characteristics This section describes the DC electrical characteristics for the MSC8101. The measurements in Table 2-4 assume the following system conditions: •...

  • Page 54: Clock Configuration

    Clock Configuration 2.6 Clock Configuration The following sections provide a general description of clock configuration. 2.6.1 Valid Clock Modes Table 2-6 shows the maximum frequency values for each rated core frequency (250, 275, or 300 MHz). The user must ensure that maximum frequency values are not exceeded. Table 2-6.
  • Page 55 Clock Configuration 2.6.2.1 System Clock Control Register Bit 0 — TYPE RESET — — DFBRG TYPE RESET — Figure 2-1. System Clock Control Register (SCCR)—0x10C80 The SCCR is memory-mapped into the SIU register map of the MSC8101. Table 2-7. SCCR Bit Descriptions Defaults Name Description...
  • Page 56 Clock Configuration Table 2-8. SCMR Bit Descriptions Defaults Name Description Settings Bit No. Hard PORESET Reset — — — Reserved 0–1 COREPDF Configuration Unaffected Core PLL Pre-Division Factor CPLL PDF= 1 2–3 Pins CPLL PDF= 2 CPLL PDF= 3 CPLL PDF= 4 COREMF Configuration Unaffected Core Multiplication Factor...

  • Page 57: Ac Timings

    AC Timings 2.7 AC Timings The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs. AC timings are based on a 50 pF load, except where noted otherwise, and 50 Ω transmission line. 2.7.1 Clocking and Timing Characteristics Table 2-9.
  • Page 58 AC Timings 2.7.2 Reset Timing The MSC8101 has several inputs to the reset logic: • Power-on reset ( PORESET • External hard reset ( HRESET • External soft reset ( SRESET Asserting an external PORESET causes concurrent assertion of an internal PORESET signal, HRESET...
  • Page 59 AC Timings Table 2-12. External Configuration Signals Description Settings RSTCONF Reset Configuration Reset Configuration Master. Input line sampled by the MSC8101 at the rising Reset Configuration Slave. edge of PORESET. DBREQ/ EONCE Event Bit 0 SC140 core starts the normal processing Input line sampled after SC140 core PLL locks.
  • Page 60 AC Timings 2.7.2.3 Host Reset Configuration Host reset configuration allows the host to program the reset configuration word via the Host port after PORESET is deasserted, as described in the MSC8101 Reference Manual. The MSC8101 samples the signals described in Table 2-12 one the rising edge of PORESET when the signal is deasserted.
  • Page 61 AC Timings Next, the MSC8101 halts until the SPLL locks. The SPLL locks according to , which are MODCK[1–3] sampled, and to MODCK_H taken from the Reset Configuration Word. SPLL locking time is 800 reference clocks, which is the clock at the output of the SPLL Pre-divider. After the SPLL is locked, all the clocks to the MSC8101 are enabled.
  • Page 62 AC Timings Figure 2-5 is a graphical representation of Table 2-14. REFCLK for 1:2, 1:3, 1:4, 1:5, 1:6 REFCLK for 1:2.5 REFCLK for 1:3.5 Figure 2-5. Internal Tick Spacing for Memory Controller Signals Note: The UPM machine and GPCM machine outputs change on the internal tick determined by the memory controller programming;...
  • Page 63 AC Timings REFCLK AACK/ARTRY/TA/TEA/DBG/BG/BR DATA bus DP input All other inputs PSDVAL/TEA/TA Address bus/Address attributes/GBL BADDR Data bus DP output Memory controller/ALE All other outputs Figure 2-6. Bus Signals 2-13...
  • Page 64 AC Timings 2.7.3.2 DMA Data Transfers Table 2-17 describes the DMA signal timing. Table 2-17. DMA Signals Number Characteristic Minimum Maximum Units DREQ setup time before REFCLK falling edge — DREQ hold time after REFCLK falling edge — DONE setup time before REFCLK rising edge —...
  • Page 65 AC Timings 1, 2 Table 2-18. Host Interface (HDI16) Timing (Continued) Number Characteristics Expression Unit Host data input setup time before write data strobe deassertion — — Host data input setup time before HACK write deassertion Host data input hold time after write data strobe deassertion —...
  • Page 66 AC Timings HA[0–3] HCS[1–2] HD[0–15] HREQ (single host request) HRRQ (double host request) Figure 2-8. Read Timing Diagram, Single Data Strobe HA[0–3] HCS[1–2] HD[0–15] HREQ (single host request) HRRQ (double host request) Figure 2-9. Read Timing Diagram, Double Data Strobe 2-16...
  • Page 67 AC Timings HA[0–3] HCS[1–2] HD[0–15] HREQ (single host request) HTRQ (double host request) Figure 2-10. Write Timing Diagram, Single Data Strobe HA[0–3] HCS[1–2] HD[0–15] HREQ (single host request) HTRQ (double host request) Figure 2-11. Write Timing Diagram, Double Data Strobe 2-17...
  • Page 68 AC Timings Figure 2-12 shows Host DMA read timing. HREQ (Output) HACK or RX[0–3] HWR, HDS, Read HRD (Input) Data HD[0–15] Valid (Output) Figure 2-12. Host DMA Read Timing Diagram Figure 2-13 shows Host DMA write timing. HREQ (Output) HACK or TX[0–3] Write HWR, HDS,...
  • Page 69 AC Timings 2.7.5 CPM Timings Table 2-19. CPM Input Characteristics Characteristic Typical Unit FCC input setup time before low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial clock input) FCC input hold time after low-to-high clock transition a. internal clock (BRGxO) b.
  • Page 70 AC Timings Serial input clock FCC inputs FCC outputs Figure 2-15. FCC External Clock Diagram BRGxO SCC/SMC/SPI/I2C inputs SCC/SMC/SPI/I2C outputs Figure 2-16. SCC/SMC/SPI/I C Internal Clock Diagram Serial input clock SCC/SMC/SPI/I2C inputs SCC/SMCSPI/I2C outputs Figure 2-17. SCC/SMC/SPI/I C External Clock Diagram Serial input clock TDM inputs TDM outputs...
  • Page 71 AC Timings Note: The timing values listed are preliminary and refer to minimum system timing requirements. Actual implementation requires conformance to the specific protocol requirements. Refer to Chapter 1 to identify the specific input and output signals associated with the referenced internal controllers and supported communication protocols.
  • Page 72 AC Timings (Input) Figure 2-21. Test Clock Input Timing Diagram (Input) Input Data Valid (Input) Output Data Valid (Output) (Output) Output Data Valid (Output) Figure 2-22. Test Access Port Timing Diagram (Input) TRST (Input) Figure 2-23. TRST Timing Diagram 2-22...

  • Page 73: Chapter 3 Packaging

    Chapter 3 Packaging 3.1 Pin-Out and Package Information This sections provides information about the MSC8101 package, including diagrams of the package pinouts and tables showing how the signals discussed in Chapter 1 are allocated. The MSC8101 is available in a 332-pin Flip Chip-Plastic Ball Grid Array (FC-PBGA). 3.2 FC-PBGA Package Description Figure 3-1 and Figure 3-2 show top and bottom views of the FC-PBGA package, including pinouts.
  • Page 74 FC-PBGA Package Description Top View IRQ5 BADDR PWE6 IRQ1 IRQ3 BADDR THERM IRQ4 THERM BADDR PWE5 IRQ2 IRQ6 VDDH VDDH VDDH VDDH VDDH VDDH VDDH PSDA IRQ7 PWE7 BCTL0 PA31 TRST VDDH VDDH VDDH BADDR BADDR PB30 PC31 PB31 PWE4 PD31 PSDA PGTA...
  • Page 75 FC-PBGA Package Description Bottom View IRQ5 BADDR PWE6 IRQ1 IRQ3 BADDR THERM IRQ4 BADDR THERM PWE5 IRQ6 IRQ2 VDDH VDDH PSDA VDDH VDDH VDDH VDDH VDDH PWE7 IRQ7 BCTL0 VDDH VDDH VDDH TRST PA31 BADDR BADDR PWE4 PB31 PC31 PB30 PD31 PSDA PWE3...
  • Page 76 FC-PBGA Package Description Table 3-1. MSC8101 Signal Listing By Name Signal Name Number AACK...
  • Page 77 FC-PBGA Package Description Table 3-1. MSC8101 Signal Listing By Name (Continued) Signal Name Number ARTRY BADDR27 BADDR28 BADDR29 BADDR30 BADDR31 BCTL0 BCTL1 BNKSEL0 BNKSEL1 BNKSEL2 BRG1O BRG1O BRG2O BRG2O BRG3O BRG4O BRG5O BRG6O BRG7O BRG8O BTM0 BTM1 CD for FCC1 CD for FCC2 CD/RENA for SCC1 CD/RENA for SCC2...
  • Page 78 FC-PBGA Package Description Table 3-1. MSC8101 Signal Listing By Name (Continued) Signal Name Number CLK3 CLK4 CLK5 CLK6 CLK7 CLK8 CLK9 CLK10 CLKIN CLKOUT COL for FCC1 COL for FCC2 CRS for FCC1 CRS for FCC2 CTS for FCC1 CTS for FCC2 CTS/CLSN for SCC1 CTS/CLSN for SCC1 CTS/CLSN for SCC2...
  • Page 79 FC-PBGA Package Description Table 3-1. MSC8101 Signal Listing By Name (Continued) Signal Name Number...
  • Page 80 FC-PBGA Package Description Table 3-1. MSC8101 Signal Listing By Name (Continued) Signal Name Number DACK1 DACK2 DACK3 DACK4 DBREQ...
  • Page 81 FC-PBGA Package Description Table 3-1. MSC8101 Signal Listing By Name (Continued) Signal Name Number DLLIN DRACK1/DONE1 DRACK2/DONE2 DREQ1 DREQ2 DREQ3 DREQ4 EXT_BG2 EXT_BG3 EXT_BR2 EXT_BR3 EXT_DBG2 EXT_DBG3 EXT1 EXT2...
  • Page 82 FC-PBGA Package Description Table 3-1. MSC8101 Signal Listing By Name (Continued) Signal Name Number 3-10...
  • Page 83 FC-PBGA Package Description Table 3-1. MSC8101 Signal Listing By Name (Continued) Signal Name Number SYN1 H8BIT HACK/HACK HCS1/HCS1 HCS2/HCS2 HD10 HD11 HD12 HD13 HD14 HD15 HDDS HDS/HDS HDSP HRD/HRD 3-11...
  • Page 84 FC-PBGA Package Description Table 3-1. MSC8101 Signal Listing By Name (Continued) Signal Name Number HREQ/HREQ HRESET HRRQ/HRRQ HTRQ/HTRQ HWR/HWR INT_OUT IRQ1 IRQ1 IRQ2 IRQ2 IRQ2 IRQ3 IRQ3 IRQ3 IRQ4 IRQ5 IRQ5 IRQ6 IRQ7 IRQ7 L1RSYNC for SI1 TDMA1 L1RSYNC for SI2 TDMB2 L1RSYNC for SI2 TDMC2 L1RSYNC for SI2 TDMD2 L1RXD for SI1 TDMA1 Serial...
  • Page 85 FC-PBGA Package Description Table 3-1. MSC8101 Signal Listing By Name (Continued) Signal Name Number L1TSYNC for SI1 TDMA1 L1TSYNC for SI2 TDMB2 L1TSYNC for SI2 TDMC2 L1TSYNC for SI2 TDMD2 L1TXD for SI1 TDMA1 Serial L1TXD for SI2 TDMB2 L1TXD for SI2 TDMC2 L1TXD for SI2 TDMD2 L1TXD0 for SI1 TDMA1 Nibble L1TXD1 for SI1 TDMA1 Nibble...
  • Page 86 FC-PBGA Package Description Table 3-1. MSC8101 Signal Listing By Name (Continued) Signal Name Number PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PB18 PB19 PB20 PB21 PB22 PB23 PB24...
  • Page 87 FC-PBGA Package Description Table 3-1. MSC8101 Signal Listing By Name (Continued) Signal Name Number PB27 PB28 PB29 PB30 PB31 PBS0 PBS1 PBS2 PBS3 PBS4 PBS5 PBS6 PBS7 PC12 PC13 PC14 PC15 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 PD16 3-15...
  • Page 88 FC-PBGA Package Description Table 3-1. MSC8101 Signal Listing By Name (Continued) Signal Name Number PD17 PD18 PD19 PD29 PD30 PD31 PGPL0 PGPL1 PGPL2 PGPL3 PGPL4 PGPL5 PGTA PORESET PPBS PSDA10 PSDAMUX PSDCAS PSDDQM0 PSDDQM1 PSDDQM2 PSDDQM3 PSDDQM4 PSDDQM5 PSDDQM6 PSDDQM7 PSDRAS PSDVAL PSDWE...
  • Page 89 FC-PBGA Package Description Table 3-1. MSC8101 Signal Listing By Name (Continued) Signal Name Number PWE2 PWE3 PWE4 PWE5 PWE6 PWE7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved RSTCONF RTS for FCC1 RTS for FCC2 RTS/TENA for SCC1 RTS/TENA for SCC2 RX_DV for FCC1 RX_DV for FCC2 RX_ER for FCC1...
  • Page 90 FC-PBGA Package Description Table 3-1. MSC8101 Signal Listing By Name (Continued) Signal Name Number RXD for FCC2 transparent/HDLC serial RXD for SCC1 RXD for SCC2 RXD0 for FCC1 MII/HDLC nibble RXD0 for FCC1 UTOPIA 8 RXD0 for FCC2 MII/HDLC nibble RXD1 for FCC1 MII/HDLC nibble RXD1 for FCC1 UTOPIA 8 RXD1 for FCC2 MII/HDLC nibble...
  • Page 91 FC-PBGA Package Description Table 3-1. MSC8101 Signal Listing By Name (Continued) Signal Name Number SPICLK SPIMISO SPIMOSI SPISEL SRESET TBST TEST TGATE1 TGATE2 THERM1 THERM2 TIN1/TOUT2 TIN2 TIN3/TOUT4 TIN4 TMCLK TOUT1 TOUT3 TRST TSIZ0 TSIZ1 TSIZ2 TSIZ3 3-19...
  • Page 92 FC-PBGA Package Description Table 3-1. MSC8101 Signal Listing By Name (Continued) Signal Name Number TX_EN for FCC1 MII TX_EN for FCC2 MII TX_ER for FCC1 MII TX_ER for FCC2 MII TXADDR0 for FCC1 UTOPIA 8 TXADDR1 for FCC1 UTOPIA 8 TXADDR2 for FCC1 UTOPIA 8 TXADDR2 for FCC1 UTOPIA 8 TXADDR3 for FCC1 UTOPIA 8...
  • Page 93 FC-PBGA Package Description Table 3-1. MSC8101 Signal Listing By Name (Continued) Signal Name Number TXD3 for FCC1 MII/HDLC nibble TXD3 for FCC1 UTOPIA 8 TXD3 for FCC2 MII/HDLC nibble TXD4 for FCC1 UTOPIA 8 TXD5 for FCC1 UTOPIA 8 TXD6 for FCC1 UTOPIA 8 TXD7 for FCC1 UTOPIA 8 TXENB for FCC1 TXPRTY for FCC1 UTOPIA 8...
  • Page 94 FC-PBGA Package Description Table 3-1. MSC8101 Signal Listing By Name (Continued) Signal Name Number Table 3-2. MSC8101 Signal Listing by Pin Designator Number Signal Name IRQ5 / DP5 / DREQ4 / EXT_DBG3 D32 / HD0 D37 / HD5 D42 / HD10 D46 / HD14 D51 / HA3 3-22...
  • Page 95 FC-PBGA Package Description Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued) Number Signal Name D55 / HREQ / HTRQ D60 / HCS2 D62 / Reserved D63 / Reserved IRQ1 / DP1 / EXT_BG2 IRQ3 / DP3 / EXT_BR3 D36 / HD4 D41 / HD9 D45 / HD13 D50 / HA2...
  • Page 96 FC-PBGA Package Description Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued) Number Signal Name D58 / HDDS DBB / IRQ3 BADDR29 / IRQ2 HPE / EE1 DBREQ / EE0 THERM2 IRQ2 / DP2 / EXT_DBG2 IRQ6 / DP6 / DACK3 D34 / HD2 D39 / HD7 D43 / HD11...
  • Page 97 FC-PBGA Package Description Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued) Number Signal Name D56 / HACK / HRRQ PSDA10 / PGPL0 MODCK1 / TC0 / BNKSEL0 PSDCAS / PGPL3 BTM1 / EE5 IRQ7 / DP7 / DACK4 D38 / HD6 PSDWE / PGPL1 PWE7 / PSDDQM7 / PBS7 MODCK2 / TC1 / BNKSEL1...
  • Page 98 FC-PBGA Package Description Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued) Number Signal Name MODCK3 / TC2 / BNKSEL2 POE / PSDRAS / PGPL2 PB30 / FCC2:MII:RX_DV / SCC2:TXD / TDBM2:L1RXD PD31 / SCC1:RXD / DRACK1 / DONE1 PC31 / BRG1O / CLK1 / TGATE1 PB31 / FCC2:MII:TX_ER / SCC2:RXD / TDMB2:L1TXD Reserved / BADDR31 / IRQ5 Reserved / BADDR30 / IRQ3...
  • Page 99 FC-PBGA Package Description Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued) Number Signal Name PWE2 / PSDDQM2 / PBS2 PWE1 / PSDDQM1 / PBS1 PWE0 / PSDDQM0 / PBS0 PA27 / FCC1:UTOPIA8:RXSOC / FCC1:MII:RX_DV PB28 / FCC2:RX_ER / FCC2:HDLC:RTS / SCC2:RTS/TENA / TDMB2:L1TSYNC PC28 / SCC2:CTS/CLSN / BRG4O / CLK4 / TIN1/TOUT2 PC27 / CLK5 / BRG5O / TGATE2 BCTL1...
  • Page 100 FC-PBGA Package Description Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued) Number Signal Name PC25 / DMA:DACK2 / BRG7O / CLK7 / TIN4 PA25 / FCC1:UTOPIA8:TXD0 / SDMA:MSNUM0 PB25 / FCC2:MII and HDLC nibble:TXD3 / TDMA1:nibble:L1TXD3 / TDMC2:L1TSYNC PC23 / EXT2 / DMA:DACK1 / CLK9 PD17 / FCC1:UTOPIA8:RXPRTY / SPI:SPIMOSI / BRG2O CLKIN PC6 / FCC1:UTOPIA8:RXADDR2 / FCC1:UTOPIA8:RXADDR2/RXCLAV1 /...
  • Page 101 FC-PBGA Package Description Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued) Number Signal Name PC22 / SI1:LIST1 / DREQ1 / CLK10 SPARE1 PA22 / FCC1:UTOPIA8:TXD3 PB18 / FCC2:MII and HDLC nibble:RXD3 / I C:SCL PA19 / FCC1:UTOPIA8:TXD6 / FCC1:MII and HDLC nibble:TXD1 PB21 / FCC2:MII and HDLC nibble:RXD0 / FCC2:transparent and HDLC serial:RXD /TDMA1:nibble:L1TXD2 / TDMD2:L1TSYNC...
  • Page 102 FC-PBGA Package Description Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued) Number Signal Name AACK PA21 / FCC1:TXD4 / FCC1:MII and HDLC nibble TXD3 PB19 / FCC2:MII and HDLC nibble RXD2 / I C:SDA PD18 / FCC1:UTOPIA8:RXADDR4 / FCC1:UTOPIA8:RXCLAV3 / SPI:SPICLK PD16 / FCC1:UTOPIA8:TXPRTY / SPI:SPIMISO RSTCONF SYN1...
  • Page 103 FC-PBGA Package Description Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued) Number Signal Name PA7 / SMC2:SMSYN / TDMA1:L1TSYNC ABB / IRQ2 TSIZ0 PA18 / FCC1:UTOPIA8:TXD7 / FCC1:MII and HDLC nibble:TXD0 / FCC1:transparent and HDLC serial:TXD PA15 / FCC1:UTOPIA8:RXD5 / FCC1:MII and HDLC nibble:RXD2 SRESET PORESET TEST...

  • Page 104: Fc-Pbga Package Mechanical Drawing

    FC-PBGA Package Mechanical Drawing 3.3 FC-PBGA Package Mechanical Drawing Notes: 1. Dimensions and tolerancing per ASME Y14.5, 1994. 2. Dimensions in millimeters. 3. Dimension b is the maximum solder ball diameter measured parallel to Datum A. 4. Primary Datum A and the seating plane are defined by the spherical crowns of the solder balls.

  • Page 105: Chapter 4 Design Considerations

    Chapter 4 Design Considerations 4.1 Thermal Design Considerations in °C can be obtained from the following: The average chip-junction temperature • θ Equation 1: T + (P where = ambient temperature °C θ °C/W = package thermal resistance junction to ambient in W ×...

  • Page 106: Electrical Design Considerations

    Electrical Design Considerations 4.2 Electrical Design Considerations The input voltage must not exceed the I/O supply by more than 2.5 V at any time, including during power-on reset. In turn, can exceed by more than 3.3 V during power-on reset, but for CCSYN no more than 100 ms.
  • Page 107 Power Considerations For an application in which external data memory is used in a 32-bit single bus mode and no other outputs are active, the core runs at 200 MHz, the CPM runs at 100 MHz and the SIU runs at 50 MHz, power dissipation is calculated as follows: Assumptions: •...

  • Page 108: Layout Practices

    Layout Practices 4.4 Layout Practices Each pin on the MSC8101 should be provided with a low-impedance path to the board’s power supply. Similarly, each pin should be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on the chip. The power supply should be bypassed to ground using at least four 0.1 µF by-pass capacitors located as closely as possible to the four sides of the package.

  • Page 109: Index

    Index coprocessor iii CPM inputs 2-20 AC timings 2-7 Address Acknowledge signal 1-10 Address Bus Busy signal 1-9 Data Bus 1-11 Address Bus signal 1-8 Data Bus Bit 32–47 signals 1-10 Address Latch Enable (ALE) 1-16 Data Bus Bit 48–51 signals 1-10 Address Retry signal 1-10 Data Bus Bit 52 signal 1-11 applications iv...
  • Page 110 Index enhanced filter coprocessor iii Host Address Line 0 signal 1-10 EOnCE Event 0(EE0) signal 1-6 Host Chip Select signal 1-11 EOnCE Event 1(EE1) signal 1-6 Host Data signal 1-10 EOnCE Event 2EE2) signal 1-6 Host Data Strobe (HDS) 1-11 EOnCE Event 3 (EE3) signal 1-6 Host Data Strobe Polarity (HDSP) 1-12 EOnCE Event 4 (EE4) signal 1-7...
  • Page 111 Index program reset configuration word via the Host port 2-10 networking capabilities iv reset causes 2-8 Non-Maskable Interrupt (NMI) 1-15 reset sources 2-8 Non-Maskable Interrupt Output(NMI_OUT) 1-15 RSTCONF 2-11 non-multiplexed bus timings soft reset 2-9 read 2-17 RSTCONF 1-7 write 2-18 SC140 core iii outputs SCC/SMC/SPI/I2C external clock diagram 2-21...
  • Page 112 Index Bus UPM General-Purpose Line 4 (PGPL4) 1-17 TAP timing diagram 2-23 Bus UPM General-Purpose Line 5 target applications iv (PGPL5) 1-17 TDM signal diagram 2-21 Data Bus Bit 48–51 (D[48–51]) 1-10 Test Clock (TCK) input timing diagram 2-23 Data Bus Bit 52 (D52) 1-11 thermal Data Bus Bit 53 (D53) 1-11 design considerations 4-1...
  • Page 116 Tai Po, N.T., Hong Kong support or sustain life, or for any other application in which the failure of the Motorola product could 852-26668334 create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola...

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