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Manuals and User Guides for Motorola DSP56009. We have
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Motorola DSP56009 manual available for free PDF download: User Manual
Motorola DSP56009 User Manual (286 pages)
24-Bit Digital Signal Processor
Brand:
Motorola
| Category:
Signal Processors
| Size: 1.21 MB
Table of Contents
Table of Contents
5
Section 1 Overview
19
Introduction
21
Manual Organization
22
Manual Conventions
23
Table 1-1 High True / Low True Signal Conventions
24
Dsp56009 Features
24
Dsp56009 Architectural Overview
26
Figure 1-1 DSP56009 Block Diagram
27
Memory and Peripheral Modules
28
DSP Core Processor
28
Data Arithmetic and Logic Unit (ALU)
29
Address Generation Unit (AGU)
29
Program Control Unit
30
Data Buses
30
Address Buses
30
Phase Lock Loop (PLL)
30
Table 1-2 Interrupt Starting Addresses and Sources
31
On-Chip Emulation (Once) Port
31
Memories
31
Program Memory
31
Table 1-3 Internal Memory Configurations
33
Data Memory
33
Y Data Memory
33
On-Chip Memory Configuration Bits
33
Bootstrap ROM
33
Table 1-4 On-Chip Peripheral Memory Map
34
External Memory
34
External Memory Interface
36
Serial Audio Interface (SAI)
37
Section 2 Signal Descriptions
39
Signal Groupings
41
Figure 2-1 DSP56009 Signals
42
Table 2-2 Power Inputs
43
Table 2-3 Grounds
43
Table 2-4 Clock and PLL Signals
44
Table 2-5 External Memory Interface (EMI) Signals
45
Table 2-6 EMI Operating States
47
Table 2-7 Interrupt and Mode Control Signals
48
Table 2-8 Serial Host Interface (SHI) Signals
52
Table 2-9 Serial Audio Interface (SAI) Receiver Signals
56
SAI Transmitter Section
58
Table 2-10 Serial Audio Interface (SAI) Transmitter Signals
58
Table 2-11 General Purpose I/O (GPIO) Signals
59
Table 2-12 On-Chip Emulation Port Signals
60
And Interrupts
65
Appendix A Bootstrap Rom Contents . . . . . . . . . . . . . . A-1
67
Introduction
67
Table 3-1 Internal Memory Configurations
67
X Data ROM
68
Table 2-1 DSP56009 Functional Group Signal Allocations
41
Reserved Memory Spaces
69
Figure 3-1 Memory Maps for PEA = 0, PEB = 0
70
Figure 3-3 Memory Maps for PEA = 0, PEB = 1
71
Dynamic Switching of Memory Configurations
72
Internal I/O Memory Map
73
Table 3-2 Internal I/O Memory Map
74
Figure 3-5 Operating Mode Register (OMR)
75
Program RAM Enable B (Peb)—Bit 3
76
Table 3-3 Operating Modes
77
Figure 3-6 Interrupt Priority Register (Address X:$FFFF)
78
Table 3-4 Interrupt Priorities
79
Table 3-5 Interrupt Vectors
80
Figure 3-7 PLL Configuration
82
Hardware Reset Operation
83
External Memory Interface
85
Introduction
87
EMI Features
88
Table 4-1 EMI Interrupt Vector
89
Table 4-2 EMI Internal Interrupt Priorities
89
Emi Programming Model
89
Figure 4-1 EMI Registers
90
EMI Base Address Registers (EBAR0 and EBAR1)
91
EMI Offset Register (EOR)
92
EMI Data Write Registers (EDWR)
93
EMI Control/Status Register (ECSR)
94
Table 4-3 EMI Memory Accesses and Locations Per Word
94
Addressing
95
EMI Word Length (Ewl[2:0])—Bits 16,2, and 1
95
Table 4-4 EMI Word Length
95
EMI Addressing Mode (Eam[3:0])—Bits 6–3
96
Table 4-5 EMI Addressing Modes
96
Table 4-6 EMI Maximum SRAM Size
97
Table 4-7 EMI Maximum DRAM Size (Relative Addressing)
98
Table 4-8 EMI Maximum DRAM Size (Absolute Addressing)
99
Table 4-9 EMI Read/Write Interrupt Select
101
EMI Data Write Register Empty (Edwe)—Bit 12
102
EMI Busy (Ebsy)—Bit 15
103
EMI Increment EBAR after Read (Einr)—Bit 7
100
EMI Interrupt Select (Eis[1:0])—Bits 9–10
101
Table 4-10 EMI DRAM Timing (Clock Cycles Per Word Transfer)
103
ESTM[3:0])— Bits 19–22
104
Table 4-11 EMI SRAM Timing (Clock Cycles Per Word Transfer)
104
EMI Enable (Eme)—Bit 23
105
Figure 4-3 EMI Refresh Control Register (ERCR)
105
EMI Refresh Clock Divider (Ecd[7:0])—Bits 0–7
106
ERCR Refresh Enable (Eref)—Bit 23
107
Figure 4-4 EMI Address Generation Block Diagram
107
SRAM Absolute Addressing
108
Table 4-12 Relative Addressing Extension Bits
108
SRAM Relative Addressing
109
Table 4-13 Word Address to Physical Address Mapping for SRAM
110
DRAM Relative Addressing
111
Table 4-14 Word-Address-To-Physical-Address Mapping for DRAM
112
Table 4-15 Address Generation for DRAM Relative Addressing
113
DRAM Absolute Addressing
114
Table 4-16 Word-To-Physical-Address Mapping for DRAM Absolute
115
Dram Refresh
115
Consideration
116
Figure 4-5 Refresh Timer Functional Diagram
117
Using the Internal Refresh Timer
117
Off Line" Refresh
118
Table 4-17 Typical DRAM Refresh Timing Requirements
119
Table 4-18 Continuous Refresh: Timings and Settings for EPS[1:0] and ECD[7:0]
120
Table 4-19 Burst Refresh: Timings and Settings for EPS[1:0] and
120
Figure 4-6 Timing Diagram of a DRAM Refresh Cycle (Fast)
121
Figure 4-7 Timing Diagram of a DRAM Refresh Cycle (Slow)
121
Emi Operating Considerations
122
Figure 4-8 EMI Pipeline
123
Read Data Transfer
124
Write-Data Transfer
127
EMI Operation During Stop
129
Figure 4-9 Illustration of the Data-Delay Structure
130
Figure 4-10 DRAM for Data Delay Buffers and for SRAM for Bootstrap
132
Emi-To-Memory Connection
132
Figure 4-11 SRAM for Data Delay Buffers and for Bootstrap
133
Figure 4-12 Replacing Drams with Srams for Large Arrays
134
Table 4-20 Maximum DSP Clock Frequencies When Using DRAM
134
Emi Timing
134
Table 4-21 Maximum DSP Clock Frequencies When Using SRAM
135
Table 4-22 Maximum DSP Clock Frequencies When Using EPROM
135
Timing Diagrams for DRAM Addressing Modes
135
Fast Timing Mode
136
Figure 4-13 Fast Read or Write DRAM Access Timing-1
136
Figure 4-14 Fast Read or Write DRAM Access Timing-2
137
Figure 4-15 Fast Read or Write DRAM Access Timing-3
138
Figure 4-16 Fast Read or Write DRAM Access Timing-4
139
Figure 4-17 Fast Read or Write DRAM Access Timing-5
140
Figure 4-18 Fast Read or Write DRAM Access Timing-6
141
Figure 4-19 Slow Read or Write DRAM Access Timing-1
142
Slow Timing Mode
142
Figure 4-20 Slow Read or Write DRAM Access Timing-2
143
Figure 4-21 Slow Read or Write DRAM Access Timing-3
144
Figure 4-22 Slow Read or Write DRAM Access Timing-4
145
Figure 4-23 Slow Read or Write DRAM Access Timing-5
146
Figure 4-24 Slow Read or Write DRAM Access Timing-6
147
Figure 4-25 SRAM Read/Write Timing
148
Timing Diagrams for SRAM Addressing Modes
148
Serial Host Interface (SHI)
149
Introduction
151
Figure 5-1 Serial Host Interface Block Diagram
152
Serial Host Interface Internal Architecture
152
Figure 5-2 SHI Clock Generator
153
Figure 5-3 SHI Programming Model-Host Side
153
Table 5-1 SHI Interrupt Vectors
155
Table 5-2 SHI Internal Interrupt Priorities
155
SHI Input/Output Shift Register (Iosr)—Host Side
156
Figure 5-5 SHI I/O Shift Register (IOSR)
156
Figure 5-6 SPI Data-To-Clock Timing Diagram
158
Table 5-3 SHI Noise Reduction Filter Mode
160
SHI Control/Status Register (HCSR)—DSP Side
161
Hm[1:0])—Bits 3–2
162
HCKR Prescaler Rate Select (Hrs)—Bit 2
159
Hdm[5:0])—Bits 8–3
160
SHI Host Receive Data FIFO (HRX)—DSP Side
157
CPHA and Cpol)—Bits 1–0
158
Table 5-4 SHI Data Size
162
Hrqe[1:0])—Bits 8–7
163
Table 5-5 HREQ Function in SHI Slave Modes
163
Table 5-6 HCSR Receive Interrupt Enable Bits
165
Host Receive FIFO Not Empty (Hrne)—Bit 17
166
HCSR Host Busy (Hbusy)—Bit 22
167
Overview
168
Figure 5-8 I 2 C Start and Stop Events
169
Figure 5-9 Acknowledgment on the I 2 C Bus
170
Figure 5-10 I
171
Figure 5-11 I
171
Shi Programming Considerations
171
SPI Slave Mode
172
SPI Master Mode
173
SHI Operation During Stop
179
HCSR Bus-Error Interrupt Enable (Hbie)—Bit 10
164
Htue)—Bit 14
165
Serial Audio Interface (SAI)
181
Introduction
183
Figure 6-1 SAI Baud-Rate Generator Block Diagram
184
Serial Audio Interface Internal Architecture
184
Figure 6-2 SAI Receive Section Block Diagram
185
Receive Section Overview
185
SAI Transmit Section Overview
186
Figure 6-3 SAI Transmit Section Block Diagram
187
Baud Rate Control Register (BRC)
189
Table 6-1 SAI Interrupt Vector Locations
189
Table 6-2 SAI Internal Interrupt Priorities
189
Figure 6-4 SAI Registers
188
Serial Audio Interface Programming Model
188
Prescale Modulus Select (Pm[7:0])—Bits 7–0
190
RCS Receiver 1 Enable (R1En)—Bit 1
191
Table 6-3 Receiver Word Length Control
191
RCS Receiver Data Shift Direction (Rdir)—Bit 6
192
Figure 6-5 Receiver Data Shift Direction (RDIR) Programming
192
Figure 6-6 Receiver Left/Right Selection (RLRS) Programming
192
RCS Receiver Clock Polarity (Rckp)—Bit 8
193
Figure 6-7 Receiver Clock Polarity (RCKP) Programming
193
Rdwt)—Bit 10
194
Figure 6-8 Receiver Relative Timing (RREL) Programming
194
Figure 6-9 Receiver Data Word Truncation (RDWT) Programming
194
RCS Receiver Interrupt Enable (Rxie)—Bit 11
195
RCS Receiver Left Data Full (Rldf)—Bit 14
196
SAI Receive Data Registers (RX0 and RX1)
197
TCS Transmitter 2 Enable (T2En)—Bit 2
198
Table 6-4 Transmitter Word Length
198
TCS Transmitter Left Right Selection (Tlrs)—Bit 7
199
Figure 6-10 Transmitter Data Shift Direction (TDIR) Programming
199
Figure 6-11 Transmitter Left/Right Selection (TLRS) Programming
199
TCS Transmitter Relative Timing (Trel)—Bit 9
200
Figure 6-12 Transmitter Clock Polarity (TCKP) Programming
200
Figure 6-13 Transmitter Relative Timing (TREL) Programming
200
TCS Transmitter Interrupt Enable (Txie)—Bit 11
201
Figure 6-14 Transmitter Data Word Expansion (TDWE) Programming
201
TCS Transmitter Interrupt Location (Txil)—Bit 12
202
TCS Transmitter Right Data Empty (Trde)—Bit 15
203
Programming Considerations
204
SAI State Machine
205
General Purpose Input/Output
207
Figure 7-1 GPIO Control/Data Register
209
Introduction
209
GPIOR Data Bits (Gd[3:0])—Bits 3–0
210
Table 7-1 GPIO Pin Configuration
210
Figure 7-2 GPIO Circuit Diagram
211
A.1 Introduction
215
A.3 Bootstrap Program Listing
216
A.4 Bootstrap Flow Chart
219
Appendix B Programming Reference
221
B.1 Introduction
223
Appendix C Application Examples
251
C.1 Introduction
253
Introduction
253
Typical System Topology
253
Typical Audio Application
254
C.4 Program Overlay
255
Program Overlay
255
Single Delay Line
255
Early Reflection Filter
256
Two Channel Comb Filter
257
3-Tap Fir Filter
260
Introduction
271
Typical System Topology
271
Typical Audio Application
272
Program Overlay
273
Single Delay Line
273
Early Reflection Filter
274
Two Channel Comb Filter
275
3-Tap Fir Filter
278
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