Figure 7-16 Crb Fsl[1:0] Bit Operation - Motorola DSP56305 User Manual

24-bit digital signal processor
Table of Contents

Advertisement

Serial Clock
RX, TX Frame SYNC
RX, TX Serial Data
NOTE: Frame sync occurs while data is valid.
Serial Clock
RX, TX Frame SYNC
RX, TX Serial Data
NOTE: Frame sync occurs for one bit time preceding the data.
Serial Clock
RX Frame Sync,
(FSR = 0)
RXSerial Data
TX Frame SYNC
TX Serial Data
Serial Clock
RX Frame SYNC
RX Serial Data
TX Frame SYNC
TX Serial Data
MOTOROLA
Enhanced Synchronous Serial Interface (ESSI)
Word Length: FSL[1:0] = 00, (SYN = 1)
Data
One Bit Length: FSL[1:0] = 10, (SYN = 1)
Data
Mixed Frame Length: FSL[1:0] = 01, (SYN = 0)
Data
Data
Mixed Frame Length: FSL[1:0] = 11, (SYN = 0)
Data
Data

Figure 7-16 CRB FSL[1:0] Bit Operation

DSP56305 User's Manual
ESSI Programming Model
Data
Data
Data
Data
Data
Data
AA0681
7-25

Advertisement

Table of Contents
loading

Table of Contents