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56303 User’s Manual 24-Bit Digital Signal Processor DSP56303UM/AD Revision 1, January 2001...
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“Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur.
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Overview Signals/Connections Memory Configuration Core Configuration Programming the Peripherals Host Interface (HI08) Enhanced Synchronous Serial Interface (ESSI) Serial Communications Interface (SCI) Triple Timer Module Bootstrap Program Programming Reference...
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Overview Signals/Connections Memory Configuration Core Configuration Programming the Peripherals Host Interface (HI08) Enhanced Synchronous Serial Interface (ESSI) Serial Communications Interface (SCI) Triple Timer Module Bootstrap Program Programming Reference...
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Timer Load Registers (TLR) ...................B-33 B-23 Host Data Direction and Host Data Registers (HDDR, HDR) ........B-34 B-24 Port C Registers (PCRC, PRRC, PDRC)..............B-35 B-25 Port D Registers (PCRD, PRRD, PDRD)..............B-36 B-26 Port E Registers (PCRE, PRRE, PDRE)..............B-37 DSP56303 User’s Manual...
You can obtain these documents—and the Motorola DSP development tools—through a local Motorola Semiconductor Sales Office or authorized distributor. To receive the latest information on this DSP, access the Motorola DSP home page at the address given on the back cover of this document.
Appendix A, Bootstrap Code—Bootstrap code and equates for the DSP56303. Appendix B, Programming Reference—Peripheral addresses, interrupt addresses, and interrupt priorities for the DSP56303; programming sheets listing the contents of the major DSP56303 registers for programmer’s reference. Manual Conventions...
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Manual Conventions Table 1-1. High True/Low True Signal Conventions (Continued) Signal/Symbol Logic State Signal State Voltage True Asserted False Deasserted Ground Note: PIN is a generic term for any pin on the chip. Ground is an acceptable low voltage level. See the appropriate data sheet for the range of acceptable low voltage levels (typically a TTL logic low).
Features Features The Motorola DSP56303, a member of the DSP56300 core family of programmable DSPs, supports wireless infrastructure applications with general filtering operations. Like the other family members, the DSP56303 uses a high-performance, single-clock-cycle- per-instruction engine (code compatible with Motorola’s popular DSP56000 core family), a barrel shifter, 24-bit addressing, instruction cache, and DMA controller.
Data arithmetic logic unit (ALU) Address generation unit Program control unit PLL and clock oscillator JTAG TAP and OnCE module Memory In addition, the DSP56303 provides a set of on-chip peripherals, discussed in Section 1.8, Peripherals, on page 1-12. Overview...
56-bit contents of either the A or B accumulator. A 56-bit result can be stored as a 24-bit operand. The LSP is either truncated or rounded into the MSP. Rounding is performed if specified. DSP56303 User’s Manual...
DSP56300 Core Functional Blocks 1.5.2 Address Generation Unit (AGU) The AGU performs the effective address calculations using integer arithmetic necessary to address data operands in memory and contains the registers that generate the addresses. It implements four types of arithmetic: linear, modulo, multiple wrap-around modulo, and reverse-carry.
A lower-frequency clock input reduces the overall electromagnetic interference generated by a system. The ability to oscillate at different frequencies reduces costs by eliminating the need to add additional oscillators to a system. DSP56303 User’s Manual...
DSP56300 Core Functional Blocks 1.5.5 JTAG TAP and OnCE Module In the DSP56300 core is a dedicated user-accessible TAP that is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture . Problems with testing high-density circuit boards led to the development of this standard under the sponsorship of the Test Technology Committee of IEEE and the JTAG.
Simultaneous glueless interface to static random access memory (SRAM) and dynamic random access memory (DRAM) Internal Buses To provide data exchange between the blocks, the DSP56303 implements the following buses: Peripheral I/O expansion bus to peripherals Program memory expansion bus to program ROM...
All internal buses on the DSP56300 family members are 24-bit buses. The program data bus is also a 24-bit bus. Figure 1-1 shows a block diagram of the DSP56303. Host Triple ESSI X Data Y Data Program RAM Interface Timer...
Peripherals Peripherals In addition to the core features, the DSP56303 provides the following peripherals: As many as 34 user-configurable GPIO signals HI08 to external hosts Dual ESSI Triple timer module Memory switch mode Four external interrupt/mode control lines 1.8.1 GPIO Functionality The GPIO port consists of up to 34 programmable signals, also used by the peripherals (HI08, ESSI, SCI, and timer).
(up to 12.5 Mbps for a 100 MHz clock). SCI asynchronous protocols include a multidrop mode for master/slave operation with wakeup on idle line and wakeup on address bit capability. This mode allows the DSP56303 to share a single serial line efficiently with other peripherals.
The DSP56303 input and output signals are organized into functional groups, as shown in Table 2-1 and illustrated in Figure 2-1. The DSP56303 operates from a 3 V supply; however, some of the inputs can tolerate 5 V. A special notice for this feature is added to the signal descriptions of those inputs.
The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[0–5]), Port D GPIO signals (PD[0–5]), and Port E GPIO signals (PE[0–2]), respectively. TIO[0–2] can be configured as GPIO signals. Figure 2-1. Signals Identified by Functional Group DSP56303 User’s Manual...
Power Power Table 2-2. Power Inputs Power Name Description PLL Power—V dedicated for use with Phase Lock Loop (PLL). The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the V power rail. Quiet Power—An isolated power for the internal processing logic.
These designations are package-dependent. Some packages connect all GND inputs except GND to each other internally. On those packages, all ground connections except GND and GND labeled GND. The numbers of connections indicated in this table are minimum values; the total GND connections are package-dependent. DSP56303 User’s Manual...
Input Input PLL Capacitor—Connects an off-chip capacitor to the PLL filter. See the DSP56303 Technical Data sheet to determine the correct PLL capacitor value. Connect one capacitor terminal to PCAP and the other terminal to V If the PLL is not used, PCAP can be tied to V , GND, or left floating.
External Memory Expansion Port (Port A) External Memory Expansion Port (Port A) Note: When the DSP56303 enters a low-power standby mode (Stop or Wait), it releases bus mastership and tri-states the relevant Port A signals: A[0–17], D[0–23], AA0/RAS0–AA3/RAS3, RD, WR, BB, CAS, BCLK, BCLK.
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Ignored Input Transfer Acknowledge—If the DSP56303 is the bus master and there is no external bus activity, or the DSP56303 is not the bus master, the TA input is ignored. The TA input is a Data Transfer Acknowledge (DTACK) function that can extend an external bus cycle indefinitely.
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CLKOUT by the internal PLL, BCLK precedes CLKOUT by one-fourth of a clock cycle. BCLK Output Tri-stated Bus Clock Not—When the DSP is the bus master, BCLK is the inverse of the BCLK signal. Otherwise, the signal is tri-stated. DSP56303 User’s Manual...
Interrupt and Mode Control Interrupt and Mode Control The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset. After is deasserted, these inputs are hardware interrupt request lines. RESET Table 2-9. Interrupt and Mode Control State During Signal Name Type...
Middle (RXM), or Receive register Low (RXL), the host interface programmer should use interrupts or poll the Receive Register Data Full (RXDF) flag that indicates data is available. This assures that the data in the receive byte registers is valid. 2-10 DSP56303 User’s Manual...
Host Interface (HI08) Table 2-10. Host Port Usage Considerations (Continued) Action Description Asynchronous write to transmit The host interface programmer should not write to the transmit byte registers, Transmit byte registers register High (TXH), Transmit register Middle (TXM), or Transmit register Low (TXL), unless the Transmit register Data Empty (TXDE) bit is set indicating that the transmit byte registers are empty.
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(HRD) after reset. PB11 Input or Port B 11—When the HI08 is configured as GPIO through the HPCR, Output this signal is individually programmed through the HDDR. This input is 5 V tolerant. 2-12 DSP56303 User’s Manual...
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Host Interface (HI08) Table 2-11. Host Interface (Continued) State During Signal Name Type Signal Description Reset or Stop HDS/HDS Input Disconnected Host Data Strobe—When the HI08 is programmed to interface with a internally single-data-strobe host bus and the HI function is selected, this signal is the Host Data Strobe (HDS) Schmitt-trigger input.
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When the HI08 is configured as GPIO through the HPCR, this signal is individually programmed through the HDDR. This input is 5 V tolerant. Note: 1. The Wait processing state does not affect the signal state. 2-14 DSP56303 User’s Manual...
Two synchronous serial interfaces (ESSI0 and ESSI1) provide a full-duplex serial port for serial communication with a variety of serial devices, including one or more industry-standard CODECs, other DSPs, microprocessors, and peripherals that implement the Motorola Serial Peripheral Interface (SPI). Table 2-12. Enhanced Synchronous Serial Interface 0 (ESSI0) State During...
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For PC5, signal direction is controlled through PRRC. This signal is configured as STD0 or PC5 through PCRC. This input is 5 V tolerant. Note: 1. The Wait processing state does not affect the signal state. 2-16 DSP56303 User’s Manual...
Enhanced Synchronous Serial Interface 1 (ESSI1) Enhanced Synchronous Serial Interface 1 (ESSI1) Table 2-13. Enhanced Synchronous Serial Interface 1 (ESSI1) State During Signal Type Signal Description Name Reset Stop SC10 Input or Input Disconnected Serial Control 0—Functions in either Synchronous or Output internally Asynchronous mode.
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For PD5, signal direction is controlled through PRRD. This signal is configured as STD1 or PD5 through PCRD. This input is 5 V tolerant. Note: 1. The Wait processing state does not affect the signal state. 2-18 DSP56303 User’s Manual...
Serial Communication Interface (SCI) 2.10 Serial Communication Interface (SCI) The Serial Communication interface (SCI) provides a full duplex port for serial communication with other DSPs, microprocessors, or peripherals such as modems. Table 2-14. Serial Communication Interface (SCI) State During Signal Type Signal Description Name...
2.11 Timers The DSP56303 has three identical and independent timers. Each can use internal or external clocking, interrupt the DSP56303 after a specified number of events (clocks), or signal an external device after counting a specific number of internal events.
JTAG/OnCE Interface 2.12 JTAG/OnCE Interface Table 2-16. JTAG/OnCE Interface State During Signal Name Type Signal Description Reset Input Input Test Clock—A test clock signal for synchronizing JTAG test logic. This input is 5 V tolerant. Input Input Test Data Input—A test data serial signal for test instructions and data.
Chapter 3 Memory Configuration Like all members of the DSP56300 core family, the DSP56303 addresses three sets of 16 M 24-bit memory internally: program, X data, and Y data. Each of these memory spaces includes both on-chip and external memory (accessed through the external memory interface).
When the instruction cache is enabled (that is, the SR[CE] bit is set), 1 K program words switch to instruction cache and are not accessible via addressing; the address range switches to external program memory. DSP56303 User’s Manual...
3.1.4 Program Bootstrap ROM The program memory space occupying locations $FF0000–$FF00BF includes the internal bootstrap ROM. This ROM contains the 192-word DSP56303 bootstrap program. X Data Memory Space The X data memory space consists of the following: Internal X data memory (2 K by default up to 3 K)
3.2.3 Internal I/O Space—X Data Memory One part of the on-chip peripheral registers and some of the DSP56303 core registers occupy the top 128 locations of the X data memory ($FFFF80–$FFFFFF). This area is referred to as the internal X I/O space and it can be accessed by MOVE, MOVEP instructions and by bit-oriented instructions (BCHG, BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET, JCLR, JSET, JSCLR and JSSET).
Dynamic Memory Configuration Switching 3.3.3 External I/O Space—Y Data Memory The off-chip peripheral registers should be mapped into the top 128 locations of Y data memory ($FFFF80–$FFFFFF in the 24-bit Address mode or $FF80–$FFFF in the 16-bit Address mode) to take advantage of the Move Peripheral Data (MOVEP) instruction and the bit-oriented instructions (BCHG, BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET, JCLR, JSET, JSCLR, and JSSET).
Sixteen-Bit Compatibility Mode Configuration Sixteen-Bit Compatibility Mode Configuration The sixteen-bit compatibility (SC) mode allows the DSP56303 to use DSP56000 object code without change. The SC bit (Bit 13 in the SR) is used to switch from the default 24-bit mode to this special 16-bit mode.
Memory Maps Memory Maps The following figures describe each of the memory space and RAM configurations defined by the settings of the SC, MS, and CE bits. The figures show the configuration and the table describes the bit settings, memory sizes, and memory locations. Default Program X Data...
Y data RAM $000000 $000000 $000000 Bit Settings Memory Configuration Addressable Program RAM X Data RAM Y Data RAM Cache Memory Size 16 M $000–$BFF $000–$7FF $000–$7FF internal not accessible Figure 3-2. Instruction Cache Enabled (0, 0, 1) DSP56303 User’s Manual...
Memory Maps Program X Data Y Data $FFFFFF $FFFFFF $FFFFFF Internal I/O External I/O $FFFF80 $FFFF80 External External Internal $FFF000 $FFF000 Reserved Internal Internal Reserved Reserved $FFF0C0 Bootstrap ROM $FF0000 $FF0000 $FF0000 External External External $000C00 $000C00 $000800 Internal Internal Internal X data RAM Y data RAM...
Bit Settings Memory Configuration Addressable Program RAM X Data RAM Y Data RAM Cache Memory Size 16 M $000–$3FF $000–$BFF $000–$BFF internal not accessible Figure 3-4. Switched Program RAM and Instruction Cache Enabled (0, 1, 1) 3-10 DSP56303 User’s Manual...
Memory Maps Program X Data Y Data $FFFF $FFFF $FFFF Internal I/O External I/O $FF80 $FF80 External External External $1000 Internal Program RAM $0800 $0800 Internal Internal X data RAM Y data RAM $0000 $0000 $0000 Bit Settings Memory Configuration Addressable Program RAM X Data RAM...
$0000 Bit Settings Memory Configuration Addressable Program RAM X Data RAM Y Data RAM Cache Memory Size 64 K $000–$BFF $000–$7FF $000–$7FF internal not accessible Figure 3-6. 16-bit Space with Instruction Cache Enabled (1, 0, 1) 3-12 DSP56303 User’s Manual...
Memory Maps Program X Data Y Data $FFFF $FFFF $FFFF Internal I/O External I/O $FF80 $FF80 External External External $0C00 $0C00 $0800 Internal Internal X data RAM Y data RAM Internal Program RAM $0000 $0000 $0000 Bit Settings Memory Configuration Addressable Program RAM X Data RAM...
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Bit Settings Memory Configuration Addressable Program RAM X Data RAM Y Data RAM Cache Memory Size 64 K $000–$3FF $000–$BFF $000–$BFF internal not accessible Figure 3-8. 16-bit Space, Switched Program RAM, Instruction Cache Enabled (1, 1, 1) 3-14 DSP56303 User’s Manual...
Chapter 4 Core Configuration This chapter presents DSP56300 core configuration details specific to the DSP56303, including: Operating modes Bootstrap program Central Processor registers — Status register (SR) — Operating mode register (OMR) Interrupt Priority Registers (IPRC and IPRP) PLL control (PCTL) register Bus Interface Unit registers —...
Operating Modes Operating Modes The DSP56303 begins operation by leaving the Reset state and going into one of eight operating modes. As the DSP56303 exits the Reset state, it loads the values of MODA MODB , and into bits MA, MB, MC, and MD of the OMR. These bit settings determine...
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Operating Modes Table 4-1. DSP56303 Operating Modes (Continued) Reset Mode MODD MODC MODB MODA Description Vector $FF0000 Bootstrap through SCI The DSP is configured to load the program RAM from the SCI interface. The number of program words to be loaded and the starting address must be specified.
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Operating Modes Table 4-1. DSP56303 Operating Modes (Continued) Reset Mode MODD MODC MODB MODA Description Vector $FF0000 HI08 bootstrap in HC11 nonmultiplexed mode The bootstrap program sets the host interface to interface with the Motorola HC11 microcontroller through the HI08. The HOST HC11 bootstrap code...
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$008000 Expanded mode Bypasses the bootstrap ROM, and the DSP56303 starts fetching instructions beginning at address $008000. Memory accesses are performed using SRAM memory access type with 31 wait states and no address attributes selected.
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Operating Modes Table 4-1. DSP56303 Operating Modes (Continued) Reset Mode MODD MODC MODB MODA Description Vector $FF0000 Bootstrap through SCI The DSP is configured to load the program RAM from the SCI interface. The number of program words to be loaded and the starting address must be specified.
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Operating Modes Table 4-1. DSP56303 Operating Modes (Continued) Reset Mode MODD MODC MODB MODA Description Vector $FF0000 HI08 bootstrap in HC11 nonmultiplexed mode The bootstrap program sets the host interface to interface with the Motorola HC11 microcontroller through the HI08. The HOST HC11 bootstrap code...
$FF0000. Software can set the mode selection bits directly in the OMR. Bootstrap modes 0 and 8 are the normal DSP56303 functioning modes. The other bootstrap modes select different specific bootstrap loading source devices. Refer to Appendix A for detailed information about the bootstrap program.
Three bytes that specify the number of (24-bit) program words to load Three bytes that specify the (24-bit) start address where the user program loads in the DSP56303 program memory The user program (three bytes for each 24-bit program word) Note: The three bytes for each data sequence are loaded least significant byte first.
During processor reset, all CCR bits are cleared. The definition of the three 8-bit registers within the SR is primarily for the purpose of compatibility with other Motorola DSPs. Bit definitions in the following paragraphs identify the bits within the SR and not within the subregister.
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Central Processor Unit (CPU) Registers Table 4-2. Status Register Bit Definitions (Continued) Bit Number Bit Name Reset Value Description Cache Enable Enables/disables the instruction cache controller. If CE is set, the cache is enabled, and instructions are cached into and fetched from the internal Program RAM.
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NOTE: Due to pipelining, a change in the SC bit takes effect only after three instruction cycles. Insert three NOP instructions after the instruction that changes the value of this bit to ensure proper operation. Reserved. Write to 0 for future compatibility. 4-12 DSP56303 User’s Manual...
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Central Processor Unit (CPU) Registers Table 4-2. Status Register Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 11–10 S[1–0] Scaling Mode Specify the scaling to be performed in the Data ALU shifter/limiter and the rounding position in the Data ALU MAC unit. The Shifter/limiter Scaling mode affects data read from the A or B accumulator registers out to the X-data bus (XDB) and Y-data bus (YDB).
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This bit is also set if a borrow is generated in a subtraction operation; otherwise, this bit is cleared. The carry or borrow is generated from Bit 55 of the result. The C bit is also affected by bit manipulation, rotate, and shift instructions. 4-14 DSP56303 User’s Manual...
RTI, or directly by the MOVEC instruction. During processor reset, the chip operating mode bits (MD, MC, MB, and MA) are loaded from the external mode select pins MODD, MODC, MODB, and MODA respectively. Table 4-3 defines the DSP56303 OMR bits. Table 4-3. Operating Mode Register (OMR) Bit Definitions...
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DSP56300 family device on the same bus. When the ABE bit is set, the BG and BB inputs are synchronized. This synchronization causes a delay between a change in BG or BB until this change is actually accepted by the receiving device. 4-16 DSP56303 User’s Manual...
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Central Processor Unit (CPU) Registers Table 4-3. Operating Mode Register (OMR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description Bus Release Timing Selects between fast or slow bus release. If BRT is cleared, a Fast Bus Release mode is selected (that is, no additional cycles are added to the access and BB is not guaranteed to be the last Port A pin that is tri-stated at the end of the access).
* The MD–MA bits reflect the corresponding value of the mode input (that is, MODD–MODA), respectively. Configuring Interrupts DSP56303 interrupt handling, like that for all DSP56300 family members, is optimized for DSP applications. Refer to the sections describing interrupts in Chapter 2, Core Architecture Overview, in the DSP56300 Family Manual.
Configuring Interrupts 4.4.1 Interrupt Priority Registers (IPRC and IPRP) There are two interrupt priority registers in the DSP56303. The IPRC (Figure 4-3) is dedicated to DSP56300 core interrupt sources, and IPRP (Figure 4-4) is dedicated to DSP56303 peripheral interrupt sources.
DSP56303 initialization program loads the table entry for each interrupt serviced with two interrupt servicing instructions. In the DSP56303, only some of the 128 vector addresses are used for specific interrupt sources. The remaining interrupt vectors are reserved and can be used for host (IPL = 3) or for host command interrupt (IPL = 2).
MF10 Figure 4-5. PLL Control Register (PCTL) Table 4-7 defines the DSP56303 PCTL bits. Changing the following bits may cause the PLL to lose lock and re-lock according to the new value: PD[3–0], PEN, XTLR, and MF. Table 4-7. PLL Control Register (PCTL) Bit Definitions...
MF[11–0] PLL Multiplication Factor Define the multiplication factor that is applied to the PLL input frequency. The MF bits are cleared during DSP56303 hardware reset and thus correspond to an MF of one. Bus Interface Unit (BIU) Registers The three Bus Interface Unit (BIU) registers configure the external memory expansion port (Port A).
When four through seven wait states are selected, one additional wait state is inserted at the end of the access. This trailing wait state increases the data hold time and the memory release time and does not increase the memory access time. 4-26 DSP56303 User’s Manual...
Bus Interface Unit (BIU) Registers Table 4-8. Bus Control Register (BCR) Bit Definitions (Continued) Bit Name Reset Value Description Number 9–5 BA1W[4–0] 11111 Bus Area 1 Wait State Control (31 wait Defines the number of wait states (one through 31) inserted into each external states) SRAM access to Area 1 (DRAM accesses are not affected by these bits).
WAIT instruction is executed, periodic refresh is still generated each time the refresh counter reaches zero. If BREN is set and a STOP instruction is executed, periodic refresh is not generated and the refresh counter is disabled. The contents of the DRAM are lost. 4-28 DSP56303 User’s Manual...
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Bus Interface Unit (BIU) Registers Table 4-9. DRAM Control Register (DCR) Bit Definitions (Continued) Reset Bit Name Description Number Value Bus Mastership Enable Enables/disables interface to a local DRAM for the DSP. When BME is cleared, the RAS and CAS pins are tri-stated when mastership is lost. Therefore, you must connect an external pull-up resistor to these pins.
BNC bits, and the external address space (X data, Y data, or program) is enabled by the AAR. Figure 4-8 shows an AAR register; Table 4-10 lists the bit definitions. Note: The DSP56303 does not support address multiplexing. BAC11 BAC10...
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2. To ensure sequential external accesses, the DMA address should advance three steps at a time in two-dimensional mode with a row length of one and an offset size of three. For details, refer to Motorola application note, APR23/D, Using the DSP56300 Direct Memory Access Controller .
DMA transfer in some of the transfer modes defined by the DTM bits. If software explicitly clears DE during a DMA operation, the channel operation stops only after the current DMA transfer completes (that is, the current word is stored into the destination). 4-32 DSP56303 User’s Manual...
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DMA Control Registers 5–0 (DCR[5–0]) Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued) Reset Bit Name Description Number Value DMA Interrupt Enable Generates a DMA interrupt at the end of a DMA block transfer after the counter is loaded with its preloaded value.
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Arbitration uses the current active DMA priority, the core priority defined by the SR bits CP[1–0], and the core-DMA priority defined by the OMR bits CDP[1–0]. Priority of core accesses to external memory is as follows: 4-34 DSP56303 User’s Manual...
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DMA Control Registers 5–0 (DCR[5–0]) Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued) Reset Bit Name Description Number Value DPR[1–0] 18–17 OMR - CDP[1–0] CP[1–0] Core Priority cont. 0 (lowest) 3 (highest) DMA accesses have higher priority than core accesses DMA accesses have the same priority as core accesses...
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(D3D = 0) addressing modes. The addressing modes are specified by the DAM bits. 9–4 DAM[5–0] DMA Address Mode Defines the address generation mode for the DMA transfer. These bits are encoded in two different ways according to the D3D bit. 4-36 DSP56303 User’s Manual...
Device Identification Register (IDR) Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued) Reset Bit Name Description Number Value 3–2 DDS[1–0] DMA Destination Space Specify the memory space referenced as a destination by the DMA. NOTE: In Cache mode, a DMA to Program memory space has some limitations (as described in Chapter 8, Instruction Cache , and Chapter 11, Operating Modes and Memory Spaces ).
4.10 JTAG Boundary Scan Register (BSR) The BSR in the DSP56303 JTAG implementation contains bits for all device signals, clock pins, and their associated control signals. All DSP56303 bidirectional pins have a corresponding register bit in the BSR for pin data and are controlled by an associated control bit in the BSR.
This chapter presents general guidelines for initializing the peripherals. These guidelines include a description of how the control registers are mapped in the DSP56303, data transfer methods that are available when the various peripherals are used, and information on General-Purpose Input/Output (GPIO) configuration.
Changes in the status bits can generate interrupt conditions. For example, the HI08 has a host status register with two host flag bits that can be encoded by the host to generate an interrupt in the DSP. DSP56303 User’s Manual...
One example would be setting an overflow flag in one of the Timers. Once the event occurs, the DSP56303 is free to continue with its next task. However, while it is waiting for the event to occur, the DSP56303 core is not executing any other code.
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Host Receive Interrupt routine location at p:$60 and executes the code there. Since this is a short interrupt, the core returns to normal code execution after executing the two move instructions, and an RTI instruction is not necessary. DSP56303 User’s Manual...
The Direct Memory Access (DMA) controller permits data transfers between internal/external memory and/or internal/external I/O in any combination without the intervention of the DSP56303 core. Dedicated DMA address and data buses and internal memory partitioning ensure that a high level of isolation is achieved so the DMA operation does not interfere with the core operation or slow it down.
5.4.4 Advantages and Disadvantages Polling is the easiest method to implement, but it requires a large amount of DSP56303 core processing power. The core cannot be involved in other processing activities while it is polling receive and transmit ready bits. Interrupts require more code, but the core can process other routines while waiting for data I/O.
Three registers control the GPIO functionality of Port B: host control register (HCR), host port GPIO data register (HDR), and host port GPIO direction register (HDDR). Chapter 6, Host Interface (HI08), discusses these registers. DSP56303 Non-Multiplexed Multiplexed Port B GPIO H[0–7]...
D direction register (PRRD), and Port D data register (PDRD). Chapter 7, Enhanced Synchronous Serial Interface (ESSI), discusses these registers. Port D GPIO DSP56303 SC1[0–2] PD[0–2] Enhanced Synchronous SCK1 Serial Interface Port 1 SRD1 (ESSI1) STD1 Figure 5-4. Port D Signals DSP56303 User’s Manual...
Three registers control the GPIO functionality of Port E: Port E control register (PCRE), Port E direction register (PRRE), and Port E data register (PDRE). Chapter 8, Serial Communication Interface (SCI), discusses these registers. DSP56303 Port E GPIO Serial Communications...
DSP Core Interface Mapping: – Registers are directly mapped into eight internal X data memory locations. Data word: – DSP56303 24-bit (native) data words are supported, as are 8-bit and 16-bit words. Handshaking protocols: – Software polled – Interrupt driven –...
– Mixed 8-bit, 16-bit, and 24-bit data transfers — DSP-to-host — Host-to-DSP – Host command Handshaking protocols: – Software polled – Interrupt-driven (Interrupts are compatible with most processors, including the MC68000, 8051, HC11, and Hitachi H8.) Data word: 8 bits DSP56303 User’s Manual...
— Thomson P6 family – Minimal glue logic (pull-ups, pull-downs) required to interface to — ISA bus — Motorola 68K family — Intel X86 family Host Port Signals The host port signals are discussed in Chapter 2, Signals/Connections. Each host port signal can be programmed as a host port signal or as a GPIO signal, PB[0–15].
In GPIO mode, two additional registers (HDDR and HDR) are related to the HI08 peripheral. The separate receive and transmit data paths are double buffered for efficient, high speed asynchronous transfers. The host-side transmit data path (host writes) is also the DSP-side DSP56303 User’s Manual...
Overview receive path; the host-side receive data path (host reads) is also the DSP-side transmit path. The Receive (RXH:RXM:RXL) and Transmit Data Registers (TXH:TXM:TXL) use the same host address. During host writes to these addresses, the data is transferred to the Transmit Data Registers while reads are performed from the Receive Data Registers.
(that is, the host has read them). The host can then use any of the available handshaking protocols to determine whether more data is ready to be read. The DSP56303 HI08 port offers the following handshaking protocols for data transfers with the host:...
HCR is set, an interrupt condition caused by the host interface sets the appropriate bit in the HSR, generating an interrupt request to the DSP56303 interrupt controller (see Figure 6-2). The DSP56303 acknowledges interrupts by jumping to the appropriate interrupt service routine.
DSP interrupt routines for execution. For example, the host may issue a command via the HI08 that sets up and enables a DMA transfer. The DSP56303 processor has reserved interrupt vector addresses for application-specific service routines. However, this flexibility is independent of the data transfer mechanisms in the HI08 and allows the host to force execution of any interrupt handler (for example, SSI, SCI, IRQx, and so on).
Operation command interrupts, the interrupt acknowledge from the DSP56303 program controller clears the pending interrupt condition. Note: When the DSP enters Stop mode, the HI08 pins are electrically disconnected internally, thus disabling the HI08 until the core leaves Stop mode. Do not issue a STOP command via the HI08 unless some other mechanism for exiting this mode is provided.
Operation 6.4.5 Endian Modes The Host Little Endian bit in the host-side Interface Control Register (ICR[5]=HLEND) allows the host to access the HI08 data registers in Big Endian or Little Endian mode. In Little Endian mode (HLEND=1), a host transfer occurs as shown in Figure 6-4. HTX/HRX Bit Number: 23 DSP side Host side...
ROM at locations $FF0000–$FF00BF of P memory. This program can load program RAM segment from the HI08 host port. When any of the modes in the preceding table are used, the core begins executing the bootstrap program and configures the HI08 based on the OMR mode bits. 6-12 DSP56303 User’s Manual...
Separate transmit and receive data registers are double-buffered to allow the DSP and host processor to transfer data efficiently at high speed. Direct memory mapping allows the DSP56303 core to communicate with the HI08 registers using standard instructions and addressing modes. In addition, the MOVEP instruction allows direct data transfers between DSP56303 internal memory and the HI08 registers or vice versa.
(HTDE) bit in the HSR is set. The HTDE bit is set when data is transferred from the HTX to the RXH, RXM, or RXL registers. If HTIE is cleared, HTDE interrupts are disabled. The bit value is indeterminate after an individual reset. 6-14 DSP56303 User’s Manual...
DSP Core Programming Model Table 6-8. Host Control Register (HCR) Bit Definitions Bit Number Bit Name Reset Value Description HRIE Host Receive Interrupt Enable Generates a host receive data interrupt request if the host receive data full (HRDF) bit in the host status register (HSR, Bit 0) is set. The HRDF bit is set when data is transferred to the HRX from the TXH, TXM, or TXL registers.
Read/write bit— The value written is the value read. Read/write bit— The value written is the value read. The corresponding signal is configured as an output and is driven with the data written to Dxx. 1. Defined by the selected configuration. 6-16 DSP56303 User’s Manual...
DSP Core Programming Model 6.6.5 Host Base Address Register (HBAR) In multiplexed bus modes, HBAR selects the base address where the host-side registers are mapped into the host bus address space. The address from the host bus is compared with the base address as programmed in the Base Address Register.
Figure 6-12. Host Port Control Register (HPCR) (X:$FFFFC4) Note: To assure proper operation of the DSP56303, the HPCR bits HAP, HRP, HCSP, HDDS, HMUX, HASP, HDSP, HROD, HAEN, and HREN should be changed only if HEN is cleared. Similarly, the HPCR bits HAP, HRP, HCSP, HDDS, HMUX, HASP, HDSP, HROD, HAEN, HREN, HCSEN, HA9EN, and HA8EN should not be set when HEN is set nor at the time HEN is set.
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DSP Core Programming Model Table 6-12. Host Port Control Register (HPCR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description HDDS Host Dual Data Strobe If the HDDS bit is cleared, the HI08 operates in single-strobe bus mode. In this mode, the bus has a single data strobe signal for both reads and writes.
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Enables/disables signals configured as GPIO. If this bit is cleared, signals configured as GPIO are disconnected: outputs are high impedance, inputs are electrically disconnected. Signals configured as HI08 are not affected by the value of HGEN. 6-20 DSP56303 User’s Manual...
6.6.7 Host Transmit (HTX) Register The HTX register is used in DSP-to-host data transfers. The DSP56303 views it as a 24-bit write-only register. Its address is X:$FFFFC7. Writing to the HTX register clears the host transfer data empty bit (HSR[HTDE]) on the DSP side. The contents of the HTX register are transferred as 24-bit data to the Receive Data Registers (RXH:RXM:RXL) when both HSR[HTDE] and receive data full (ISR[RXDF]) on the host-side bits are cleared.
6.6.8 Host Receive (HRX) Register The HRX register is used in host-to-DSP data transfers. The DSP56303 views it as a 24-bit read-only register. Its address is X:$FFFFC6. It is loaded with 24-bit data from the transmit data registers (TXH:TXM:TXL on the host side) when both the transmit data register empty (ISR[TXDE]) on the host side and host receive data full (HSR[HRDF]) on the DSP side are cleared.
I/O instruction rate without testing the handshake flags for each transfer. If full handshake is not needed, the host processor can treat the DSP56303 as a fast device, and data can be transferred between the host processor and the DSP56303 at the fastest data rate of the host processor.
Host Flag 1 A general-purpose flag for host-to-DSP communication. The host processor can set or clear HF1, and the DSP56303 can not change it. HF1 is reflected in the HSR on the DSP side of the HI08. Host Flag 0 A general-purpose flag for host-to-DSP communication.
6.7.2 Command Vector Register (CVR) The host processor uses the CVR, an 8-bit read/write register, to cause the DSP56303 to execute an interrupt. The host command feature is independent of any of the data transfer mechanisms in the HI08. It causes execution of any of the 128 possible interrupt routines in the DSP core.
The host processor uses the HC bit to handshake the execution of host command interrupts. Normally, the host processor sets HC to request a host command interrupt from the DSP56303. When the DSP56303 acknowledges the host command interrupt, HI08 hardware clears the HC bit.
DSP side of the HI08. This feature has many applications. For example, if the host processor issues a host command that causes the DSP56303 to read the HRX, the host processor can be guaranteed that the data it just transferred to the HI08 is that being received by the DSP56303.
Receive Data Register Full Indicates that the receive byte registers (RXH:RXM:RXL) contain data from the DSP56303 to be read by the host processor. RXDF is set when the HTX is transferred to the receive byte registers. RXDF is cleared when the host processor reads the receive data register (RXL or RXH according to HLEND bit).
Writing to the data register at host address $7 clears the ISR[TXDE] bit. The contents of the transmit byte registers are transferred as 24-bit data to the HRX register when both ISR[TXDE] and HSR[HRDF] are cleared. This transfer operation sets HSR[TXDE] and HSR[HRDF]. 6-30 DSP56303 User’s Manual...
Host Programmer Model Note: The external host should never write to the TXH:TXM:TXL registers if the ISR[TXDE] bit is cleared. Note: When data is written to a peripheral device, there is a two-cycle pipeline delay until any status bits affected by this operation are updated. If you read any of those status bits within the next two cycles, the bit will not reflect its current status.
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Programming Model Quick Reference Table 6-19. HI08 Programming Model, DSP Side (Continued) Reset Type Register Indivi- Name Value Function STOP dual HROD Host Request HREQ/HTRQ/HRRQ = driven HPCR Open Drain HREQ/HTRQ/HRRQ = open drain HDSP Host Data Strobe HDS/HRD/HWR active low —...
ESSI clock generator. There are two independent and identical ESSIs in the DSP56303: ESSI0 and ESSI1. For simplicity, a single generic ESSI is described here. The ESSI block diagram is shown in Figure 7-1. This interface is synchronous because all serial transfers are synchronized to one clock.
On-Demand mode is for nonperiodic transfers of data. This mode, which offers a subset of the Motorola Serial Peripheral Interface (SPI) protocol, can transfer data serially at high speed when the data become available. Since each ESSI unit can be configured with one receiver and three transmitters, the two units can be used together for surround sound applications (which need two digital input channels and six digital output channels).
ESSI Data and Control Signals ESSI Data and Control Signals Three to six signals are required for ESSI operation, depending on the operating mode selected. The serial transmit data ( ) signal and serial control ( ) signals are fully synchronized to the clock if they are programmed as transmit-data signals. 7.2.1 Serial Transmit Data Signal (STD) signal transmits data from the serial transmit shift register.
CODECs or decoded externally to select up to four CODECs. If is configured as a serial flag or receive frame sync signal, the Serial Control Direction 1 CRB[SCD1] bit determines its direction. DSP56303 User’s Manual...
ESSI individual reset allows a program to reset each interface separately from the other internal peripherals. During ESSI individual reset, internal DMA accesses to the data registers of the ESSI are not valid, and data read there are undefined. To ensure proper operation of the DSP56303 User’s Manual...
Operation ESSI, use an ESSI individual reset when you change the ESSI control registers (except for bits TEIE, REIE, TLIE, RLIE, TIE, RIE, TE2, TE1, TE0, and RE). Here is an example of how to initialize the ESSI. Put the ESSI in its individual reset state by clearing the PCR bits. Configure the control registers (CRA, CRB) to set the operating mode.
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Write to all the enabled TX registers or to the TSR to clear this interrupt. This error-free interrupt uses a fast interrupt service routine for minimum overhead (if no more than two transmitters are used). DSP56303 User’s Manual...
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Operation To configure an ESSI exception, perform the following steps: Configure the interrupt service routine (ISR): Load vector base address register VBA (b23:8) Define I_VEC to be equal to the VBA value (if that is nonzero). If it is defined, I_VEC must be defined for the assembler before the interrupt equate file is included.
When the ESSI transmits data in On-Demand mode (that is, MOD = 1 in the CRB and DC[4–0]=$00000 in the CRA) with WL[2–0] = 100, the transmission does not work properly. To ensure correct operation, do not use On-Demand mode with the WL[2–0] = 100 32-bit word length mode. 7-10 DSP56303 User’s Manual...
If CRB[FSL1] is cleared, the receive frame sync is asserted during the entire data transfer period. This frame sync length is compatible with Motorola codecs, serial peripherals that conform to the Motorola SPI, serial A/D and D/A converters, shift registers, and telecommunication pulse code modulation serial I/O.
Frames do not have to be adjacent; that is, a new frame sync does not have to follow the previous frame immediately. Gaps of arbitrary periods can occur between frames. All the enabled transmitters are tri-stated during these gaps. 7-12 DSP56303 User’s Manual...
The value on SC[1–0] is stable from the time the first bit of the transmit data word transmits until the first bit of the next transmit data word transmits. Software can directly set the OF[1–0] values, allowing the DSP56303 to control data transmission by indirectly controlling the value of the SC[1–0] flags.
ESSI. CRA controls the ESSI clock generator bit and frame sync rates, word length, and number of words per frame for serial data. SSC1 —Reserved bit; read as 0; write to 0 for future compatibility. (ESSI0 X:$FFFFB5, ESSI1 X:$FFFFA5) Figure 7-2. ESSI Control Register A(CRA) 7-14 DSP56303 User’s Manual...
ESSI Programming Model Table 7-3. ESSI Control Register A (CRA) Bit Definitions Bit Number Bit Name Reset Value Description Reserved. Write to 0 for future compatibility. SSC1 Select SC1 Controls the functionality of the SC1 signal. If SSC1 is set, the ESSI is configured in Synchronous mode (the CRB synchronous/asynchronous bit (SYN) is set), and transmitter 2 is disabled (transmit enable (TE2) = 0), then the SC1 signal acts as the transmitter 0 driver-enabled signal while the SC1...
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This definition is reversed from that of the SSI in other DSP56000 family members. The maximum allowed internally generated bit clock frequency is the internal DSP56303 clock frequency divided by 4; the minimum possible internally generated bit clock frequency is the DSP56303 internal clock frequency divided by 4096.
(or the Time Slot Register (TSR)) before you set the TE bit. The normal transmit disable sequence is to set the Transmit Data Empty (TDE) bit and then to clear the TE, Transmit Interrupt Enable (TIE), and Transmit Exception Interrupt 7-18 DSP56303 User’s Manual...
ESSI Programming Model Enable (TEIE) bits. In Network mode, if you clear the appropriate TE bit and set it again, then you disable the corresponding transmitter (0, 1, or 2) after transmission of the current data word. The transmitter remains disabled until the beginning of the next frame. During that time period, the corresponding SC (or in the case of TX0) signal remains in a high-impedance state.
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TE0 can be left enabled. NOTE: Transmitter 0 is the only transmitter that can operate in Asynchronous mode (SYN = 0). The setting of the TE0 bit does not affect the generation of frame sync or output flags. 7-20 DSP56303 User’s Manual...
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ESSI Programming Model Table 7-4. ESSI Control Register B (CRB) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description Transmit 1 Enable Enables the transfer of data from TX1 to Transmit Shift Register 1. TE1 is functional only when the ESSI is in Synchronous mode and is ignored when the ESSI is in Asynchronous mode.
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The internal clock is output on the SCK signal. When SCKD is cleared, the external clock source is selected. The internal clock generator is disconnected from the SCK signal, and an external clock source may drive this signal. 7-22 DSP56303 User’s Manual...
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ESSI Programming Model Table 7-4. ESSI Control Register B (CRB) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description SCD2 Serial Control Direction 2 Controls the direction of the SC2 I/O signal. When SCD2 is set, SC2 is an output;...
Mixed Frame Length: FSL1 = 1, FSL0 = 1 Serial Clock RX Frame SYNC RX Serial Data Data Data TX Frame SYNC TX Serial Data Data Data Figure 7-6. CRB FSL0 and FSL1 Bit Operation (FSR = 0) 7-24 DSP56303 User’s Manual...
ESSI Programming Model Asynchronous (SYN = 0) Transmitter Frame Clock SYNC External Transmit Clock External Transmit Frame Internal Clock Internal Frame SYNC ESSI Bit Clock External Receive Clock External Receive Frame Clock Frame SYNC Receiver NOTE: Transmitter and receiver may have different clocks and frame syncs. SYNCHRONOUS (SYN = 1) Transmitter Frame...
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Normal Mode (MOD = 0) Serial Clock SSI Control Register B (CRB) (READ/WRITE) Frame SYNC Transmitter Interrupt (or DMA Request) and Serial Data Data Data Receiver Interrupt (or DMA Request) and Flags NOTE: Interrupts occur and data is transferred once per frame sync. Network Mode (MOD = 1) Serial Clock Frame SYNC...
DSP transmit underrun error interrupt request is issued when the TUE bit is set. The programmer can also clear TUE by first reading the SSISR with the TUE bit set, then writing to all the enabled transmit data registers or to the TSR. 7-28 DSP56303 User’s Manual...
ESSI Programming Model Table 7-5. ESSI Status Register (SSISR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description Receive Frame Sync Flag When set, the RFS bit indicates that a receive frame sync occurred during the reception of a word in the serial receive data register. In other words, the data word is from the first time slot in the frame.
When ALC is set, the MSB is Bit 15 and the most significant byte is unused. Unused bits are read as 0. Data shifts out of these registers MSB first if the SHFD bit is cleared and LSB first if SHFD is set. 7-30 DSP56303 User’s Manual...
ESSI Programming Model 16 15 ESSI Receive Data Receive High Byte Receive Middle Byte Receive Low Byte Register 16 15 Serial Receive Receive High Byte Receive Middle Byte Receive Low Byte Shift Register 24 Bit 16 Bit 12 Bit 8 Bit WL1, WL0 Least Significant 8-bit Data...
24-bit Data NOTES: (b) Transmit Registers Data is received MSB first if SHFD = 0. 4-bit fractional format (ALC = 0). 32-bit mode is not shown. Figure 7-13. ESSI Data Path Programming Model (SHFD = 1) 7-32 DSP56303 User’s Manual...
ESSI Programming Model 7.5.7 ESSI Transmit Data Registers (TX[2–0]) ESSI0:TX20, TX10, TX00; ESSI1:TX21, TX11, TX01 TX2, TX1, and TX0 are 24-bit write-only registers. Data written into these registers automatically transfers to the transmit shift registers. (See Figure 7-12 and Figure 7-13.) The data transmitted (8, 12, 16, or 24 bits) is aligned according to the value of the ALC bit.
TSM setting. If the TSM is read, it shows the current setting. After a hardware signal or software RESET instruction, the TSM register is reset to RESET $FFFFFFFF, enabling all 32 slots for data transmission. 7-34 DSP56303 User’s Manual...
ESSI Programming Model 7.5.10 Receive Slot Mask Registers (RSMA, RSMB) Both receive slot mask registers are read/write registers. In Network mode, the receiver(s) use these registers to determine which action to take in the current time slot. Depending on the setting of the bits, the receiver(s) either tri-state the receiver(s) data signal(s) or receive a data word and generate a receiver full condition.
PC[5–0] and the ESSI signals are STD0, SRD0, SCK0, and SC0[2–0]. For ESSI1, the GPIO signals are PD[5–0] and the ESSI signals are STD1, SRD1, SCK1, and SC1[2–0]. = Reserved. Read as zero. Write with zero for future compatibility. Figure 7-18. Port Control Registers (PCRC X:$FFFFBF) (PCRD X:$FFFAF) 7-36 DSP56303 User’s Manual...
GPIO Signals and Registers 7.6.2 Port Direction Registers (PRRC and PRRD) The read/write PRRC and PRRD control the data direction of the ESSI0 and ESSI1 GPIO signals when they are enabled by the associated Port Control Register (PCRC or PCRD, respectively).
PC[5–0]. For ESSI1, the GPIO signals are PD[5–0]. The corresponding data bits for Port C GPIOs are PDRC[5–0]. The corresponding data bits for Port D GPIOs are PDRD[5–0]. = Reserved. Read as zero. Write with zero for future compatibility. Figure 7-20. Port Data Registers (PDRC X:$FFFFBD) (PDRD X: $FFFFAD) 7-38 DSP56303 User’s Manual...
SCI asynchronous protocols include a multidrop mode for master/slave operation with wake-up on idle line and wake-up on address bit capability. This mode allows the DSP56303 to share a single serial line efficiently with other peripherals.
All receivers check for an address match at the start of each message. Receivers with no address match can ignore the remainder of the message and use a wakeup mode to enable the receiver at the start of the next message. Receivers with an address match can receive the DSP56303 User’s Manual...
I/O Signals message and optionally transmit an acknowledgment to the sender. The particular message format and protocol used are determined by the user’s software. 8.1.3.1 Transmitting Data and Address Characters To send data, the 8-bit data character must be written to the STX register. Writing the data character to the STX register sets the ninth bit in the frame to zero, which indicates that this frame contains data.
, since the clock does not need to be transmitted in Asynchronous mode. Because SCLK is independent of SCI data I/O, there is no connection between programming the signal as and data coming out the signal. SCLK DSP56303 User’s Manual...
SCI After Reset SCI After Reset There are several different ways to reset the SCI: Hardware signal RESET Software RESET instruction: Both hardware and software resets clear the port control register bits, which configure all I/O as GPIO input. The SCI remains in the Reset state as long as all SCI signals are programmed as GPIO ( , and all are cleared);...
SCI. When the SCI is configured in Synchronous mode, internal clock, and all the SCI pins are simultaneously enabled, an extra pulse of one DSP clock length is provided on the pin. SCLK DSP56303 User’s Manual...
SCI Initialization There are two workarounds for this issue: Enable an SCI pin other than SCLK In the next instruction, enable the remaining SCI pins, including the pin. SCLK Following is an example of one way to initialize the SCI: Ensure that the SCI is in its individual reset state (PCRE = $0).
SCI idle line occurs when the receive line enters the idle state (10 or 11 bits of ones). This interrupt is latched and then automatically reset when the interrupt is accepted. This interrupt is enabled by SCR[10] (ILIE). DSP56303 User’s Manual...
SCI Programming Model SCI timer occurs when the baud rate counter reaches zero. This interrupt is automatically reset when the interrupt is accepted. This interrupt is enabled by SCR[13] (TMIE). SCI Programming Model The SCI programming model can be viewed as three types of registers: Control —...
2. D0 = LSB; D7 = MSB 3. Data is transmitted and received LSB first if SSFTD = 0, or MSB first if SSFTD = 1 Figure 8-1. SCI Data Word Formats (SSFTD = 1), 1 8-10 DSP56303 User’s Manual...
32. Either a hardware RESET signal or a software RESET instruction clears this bit. To ensure proper operation of the timer, STIR must not be changed during timer operation (that is, if TMIE = 1). 8-12 DSP56303 User’s Manual...
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SCI Programming Model Table 8-2. SCI Control Register (SCR) Bit Definitions (Continued) Reset Bit Name Description Number Value TMIE Timer Interrupt Enable Enables/disables the SCI timer interrupt. If TMIE is set, timer interrupt requests are sent to the interrupt controller at the rate set by the SCI clock register. The timer interrupt is automatically cleared by the timer interrupt acknowledge from the interrupt controller.
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An external pullup resistor is required on the bus. When WOMS is cleared, the TXD signal uses an active internal pullup. Either a hardware RESET signal or a software RESET instruction clears WOMS. 8-14 DSP56303 User’s Manual...
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SCI Programming Model Table 8-2. SCI Control Register (SCR) Bit Definitions (Continued) Reset Bit Name Description Number Value Receiver Wakeup Enable When RWU is set and the SCI is in Asynchronous mode, the wakeup function is enabled; i. e., the SCI is asleep and can be awakened by the event defined by the WAKE bit.
SCI Programming Model 8.6.2 SCI Status Register (SSR) The SSR is a read-only register that indicates the status of the SCI. IDLE RDRF TDRE TRNE —Reserved bit; read as 0; write to 0 for future compatibility. Table 8-3. SCI Status Register Table 8-4.
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STX or STXA is transmitted next. That is, there is no word in the transmit shift register being transmitted. This procedure is useful when initiating the transfer of a message (that is, a string of characters). 8-18 DSP56303 User’s Manual...
SCI Programming Model 8.6.3 SCI Clock Control Register (SCCR) The SCCR is a read/write register that controls the selection of clock modes and baud rates for the transmit and receive sections of the SCI interface. The SCCR is cleared by a hardware signal.
SCI Programming Model As noted in Section 8.6.1, the SCI can be configured to operate in a single Synchronous mode or one of five Asynchronous modes. Synchronous mode requires that the TX and RX clocks use the same source, but that source may be the internal SCI clock if the SCI is configured as a master device or an external clock if the SCI is configured as a slave device.
The SRX can be read at three locations as SRXL, SRXM, and SRXH. When SRXL is read, the contents of the SRX are placed in the lower byte of the data bus and the remaining bits on 8-22 DSP56303 User’s Manual...
SCI Programming Model the data bus are read as zeros. Similarly, when SRXM is read, the contents of SRX are placed into the middle byte of the bus, and when SRXH is read, the contents of SRX are placed into the high byte with the remaining bits are read as 0s.
For bits 2–0, a 0 selects PEn as the signal and a 1 selects the specified SCI signal. = Reserved. Read as zero. Write to zero for future compatibility. Figure 8-8. Port E Control Register (PCRE X:$FFFF9F) 8-24 DSP56303 User’s Manual...
GPIO Signals and Registers 8.7.2 Port E Direction Register (PRRE) The read/write PRRE controls the direction of SCI GPIO signals. When port signal[i] is configured as GPIO, PRRE[i] controls the port signal direction. When PRRE[i] is set, the GPIO port signal[i] is configured as output. When PRRE[i] is cleared, the GPIO port signal[i] is configured as input.
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GPIO Signals and Registers 8-26 DSP56303 User’s Manual...
Chapter 9 Triple Timer Module The timers in the DSP56303 internal triple timer module act as timed pulse generators or as pulse-width modulators. Each timer has a single signal that can function as a GPIO signal or as a timer signal. Each timer can also function as an event counter to capture an event or to measure the width or period of a signal.
9.1.2 Individual Timer Block Diagram Figure 9-2 shows the structure of an individual timer block. The DSP56303 treats each timer as a memory-mapped peripheral with four registers occupying four 24-bit words in the X data memory space. The three timers are identical in structure and function. Either standard polled or interrupt programming techniques can be used to service the timers.
Operation The timer mode is controlled by the TC[3–0] bits which are TCSR[7–4]. For a listing of the timer modes and descriptions of their operations, see Section 9.3, Operating Modes, on page 9-5. TCSR TCPR Control/Status Load Count Compare Register Register Register Register...
Define I_VEC to be equal to the VBA value (if that is nonzero). If it is defined, I_VEC must be defined for the assembler before the interrupt equate file is included. Load the exception vector table entry: two-word fast interrupt, or jump/branch to subroutine (long interrupt). p:TIM0C DSP56303 User’s Manual...
Operating Modes Configure the interrupt trigger: Enable and prioritize overall peripheral interrupt functionality. IPRP (TOL[1–0]) Enable a specific peripheral interrupt. TCSR0 (TCIE) Unmask interrupts at the global level. SR (I[1–0]) Configure a peripheral interrupt-generating function. TCSR0 (TC[7–4]) Enable peripheral and associated signals. TCSR0 (TE) Operating Modes Each timer has operating modes that meet a variety of system requirements, as follows:...
If the TCSR[TRM] bit is set, the counter is reloaded with the TLR value at the next timer clock and the count is resumed. If TCSR[TRM] is cleared, the counter continues to increment on each timer clock signal. This process repeats until the timer is disabled. DSP56303 User’s Manual...
Operating Modes Mode 2 (internal clock): TRM = 0 first event N = write preload M = write compare Clock (CLK/2 or prescale CLK) N + 1 M + 1 Counter (TCR) TCPR TCF (Compare Interrupt if TCIE = 1) TIO pin (INV = 0) First toggle = M - N clock periods Second and later toggles = 2...
DSP56303 internal operating frequency divided by 4. The value of the TCSR[INV] bit determines whether low-to-high (0 to 1) transitions or high-to-low (1 to 0) transitions increment the counter.
Operating Modes Mode 3 (internal clock): TRM = 0 if clock source is from TIO pin, TIO < CPUCLK + 4 N = write preload first event M = write compare Clock (TIO pin or prescale CLK) N + 1 M + 1 Counter (TCR) TCPR...
TCSR[TRM] bit is set, the counter is loaded with the TLR value on the first timer clock received following the next valid transition on the input signal, and the count resumes. If TCSR[TRM] is cleared, the counter continues to increment on each timer clock. This process repeats until the timer is disabled. 9-14 DSP56303 User’s Manual...
Operating Modes Mode 4 (internal clock): TRM = 1 first event N = write preload M = write compare Clock (CLK/2 or prescale CLK) N + 1 Counter N + 1 Next 0-to-1 edge on TIO loads counter and process repeats width being measured TIO pin Interrupt Service...
NOTE: If INV = 1, a 1-to-0 edge on TIO loads the counter, and a 0-to-1 edge on TIO loads TCR with count and the counter with N. Figure 9-13. Period Measurement Mode, TRM = 1 9-16 DSP56303 User’s Manual...
Operating Modes first event Mode 5 (internal clock): TRM = 0 N = write preload M = write compare Clock (CLK/2 or prescale CLK) N + 1 M + 1 Counter Counter continues counting, does N + 1 not stop. Overflow may occur (TOF=1).
= M - N clock TCF (Compare Interrupt if TCIE = 1) periods NOTE: If INV = 1, a 1-to-0 edge on TIO loads TCR with count and stops the counter. Figure 9-15. Capture Measurement Mode, TRM = 0 9-18 DSP56303 User’s Manual...
Operating Modes 9.3.3 Pulse Width Modulation (PWM, Mode 7) Bit Settings Mode Characteristics Mode Name Function Clock Pulse width modulation Output Internal In Mode 7, the timer generates periodic pulses of a preset width. When the counter equals the value in the TCPR, the output signal is toggled and TCSR[TCF] is set.
TCSR[TE] bit is set. In Mode 9, internal logic preserves the value and direction for an additional 2.5 internal clock cycles after the hardware signal is RESET asserted. This convention ensures that a valid signal is generated when the signal RESET resets the DSP56303. 9-22 DSP56303 User’s Manual...
Operating Modes (Software does not reset watchdog timer; watchdog times out) Mode 9 (internal clock): TRM = 0 first event TRM = 1 is not useful for watchdog function N = write preload M = write compare Clock (CLK/2 or prescale CLK) M + 1 Counter (TCR) N + 1...
TIO pin (INV = 1) TIO can connect to the RESET pin, internal hardware preserves the TIO value and direction for an additional 2.5 clocks to ensure a reset of valid length. Figure 9-19. Watchdog Toggle Mode 9-24 DSP56303 User’s Manual...
Any external changes that happen to the signals are ignored when the DSP56303 is in stop state. To ensure correct operation, disable the timers before the DSP56303 is placed in stop state. 9.3.6 DMA Trigger Each timer can also trigger DMA transfers if a DMA channel is programmed to be triggered by a timer event.
TIO signal. The external clock is internally synchronized to the internal clock. The external clock frequency must be lower than the DSP56303 internal operating frequency divided by 4 (that is, CLK/4).
Reserved. Read as 0. Write to 0 for future compatibility Figure 9-23. Timer Control/Status Register (TCSR) Table 9-3. Timer Control/Status Register (TCSR) Bit Definitions Bit Number Bit Name Reset Value Description 23–22 Reserved. Write to zero for future compatibility. 9-28 DSP56303 User’s Manual...
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Triple Timer Module Programming Model Table 9-3. Timer Control/Status Register (TCSR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description Timer Compare Flag Indicate that the event count is complete. In timer, PWM, and watchdog modes, the TCF bit is set after (M – N + 1) events are counted. (M is the value in the compare register and N is the TLR value.) In measurement modes, the TCF bit is set when the measurement completes.
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NOTE: The INV bit affects both the timer and GPIO modes of operation. To ensure correct operation, change this bit only when one or both of the following conditions is true: the timer is disabled (the TCSR[TE] bit is cleared). The timer is in GPIO mode. 9-30 DSP56303 User’s Manual...
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Triple Timer Module Programming Model Table 9-3. Timer Control/Status Register (TCSR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 7–4 TC[3–0] Timer Control Control the source of the timer clock, the behavior of the TIO signal, and Operating Modes the Timer mode of operation.
TIO signal. signal from the TIO signal. Counter is incremented on Counter is incremented on the rising edge of the signal the falling edge of the from the TIO signal. signal from the TIO signal. — — 9-32 DSP56303 User’s Manual...
Triple Timer Module Programming Model Table 9-4. Inverter (INV) Bit Operation (Continued) TIO Programmed as Input TIO Programmed as Output Mode INV = 0 INV = 1 INV = 0 INV = 1 Width of the high input Width of the low input pulse is measured.
Appendix A Bootstrap Program This appendix lists the bootstrap program and equates for the DSP56303. Motorola posts updates to the bootstrap program on the Worldwide Web at the following URL: http://www.mot.com/SPS/DSP/tools/other.html Bootstrap Code ; BOOTSTRAP CODE FOR DSP56303 - (C) Copyright 1995 Motorola Inc.
; specifying the address to start loading the program words and then 3 bytes ; forming 24-bit words for each program word to be loaded. ; The program words will be stored in contiguous PRAM memory locations ; starting at the specified starting address. DSP56303 User’s Manual...
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Bootstrap Code ; After reading the program words, program execution starts from the same ; address where loading started. ; The Host Interface bootstrap load program may be stopped by setting the ; Host Flag 0 (HF0). This will start execution of the loaded program from ;...
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; HAEN = 0 Host acknowledge is disabled ; HREN = 1 Host requests are enabled ; HCSEN = 1 Host chip select input enabled ; HA9EN = 0 (address 9 enable bit has no meaning in DSP56303 User’s Manual...
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Bootstrap Code non-multiplexed bus) ; HA8EN = 0 (address 8 enable bit has no meaning in non-multiplexed bus) ; HGEN = 0 Host GPIO pins are disabled <HI08CONT HC11HOSTLD movep #%0000001000011000,x:M_HPCR ; Configure the following conditions: ; HAP = 0 Negative host acknowledge ;...
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<FINISH ;======================================================================== EPRSCILD jclr #1,omr,EPROMLD ; If MC:MB:MA=001, go load from EPROM ;======================================================================== ; This is the routine that loads from the SCI. ; MC:MB:MA=010 - external SCI clock SCILD movep #$0302,X:M_SCR ; Configure SCI Control Reg DSP56303 User’s Manual...
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Bootstrap Code movep #$C000,X:M_SCCR ; Configure SCI Clock Control Reg movep #7,X:M_PCRE ; Configure SCLK, TXD and RXD do #6,_LOOP6 ; get 3 bytes for number of ; program words and 3 bytes ; for the starting address jclr #2,X:M_SSR,* ;...
; Port D Direction Data Register M_PDRD $FFFFAD ; Port D GPIO Data Register M_PCRE $FFFF9F ; Port E Control register M_PRRE $FFFF9E ; Port E Direction Register M_PDRE $FFFF9D ; Port E Data Register M_OGDB $FFFFFC ; OnCE GDB Register ;------------------------------------------------------------------------ DSP56303 User’s Manual...
Direct Memory Access (DMA) Equates Timer Prescaler Register Bit Flags M_PS EQU $600000 ; Prescaler Source Mask M_PS0 M_PS1 Timer Control Bits M_TC0 ; Timer Control 0 M_TC1 ; Timer Control 1 M_TC2 ; Timer Control 2 M_TC3 ; Timer Control 3 ;------------------------------------------------------------------------ Direct Memory Access (DMA) Equates EQUATES for Direct Memory Access (DMA)
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;Channel Transfer Done Status MASK M_DTD0 ; DMA Channel Transfer Done Status 0 M_DTD1 ; DMA Channel Transfer Done Status 1 M_DTD2 ; DMA Channel Transfer Done Status 2 M_DTD3 ; DMA Channel Transfer Done Status 3 A-16 DSP56303 User’s Manual...
; Number of Address Bits to Compare Mask M_BAC $FFF000 ; Address to Compare Bits Mask BAC(11:0) control and status bits in SR M_CP $c00000 ; mask for CORE-DMA priority bits in SR M_CA ; Carry A-18 DSP56303 User’s Manual...
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Bus Interface Unit (BIU) Equates ; Overflow ; Zero ; Negative ; Unnormalized ; Extension ; Limit ; Scaling Bit M_I0 ; Interrupt Mask Bit 0 M_I1 ; Interrupt Mask Bit 1 M_S0 ; Scaling Mode Bit 0 M_S1 ; Scaling Mode Bit 1 M_SC ;...
Table B-4, Interrupt Source Priorities Within an IPL, on page B-10 lists the priorities of specific interrupts within interrupt priority levels. The programming sheets appear in this manual as figures (listed in Table B-1); they show the major programmable registers on the DSP56303. Programming Reference...
ESSI0 Receive Data VBA:$32 0–2 ESSI0 Receive Data With Exception Status VBA:$34 0–2 ESSI0 Receive Last Slot VBA:$36 0–2 ESSI0 Transmit Data VBA:$38 0–2 ESSI0 Transmit Data With Exception Status VBA:$3A 0–2 ESSI0 Transmit Last Slot VBA:$3C 0–2 Reserved DSP56303 User’s Manual...
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Interrupt Sources and Priorities Table B-3. Interrupt Sources (Continued) Interrupt Interrupt Priority Interrupt Source Starting Address Level Range VBA:$3E 0–2 Reserved VBA:$40 0–2 ESSI1 Receive Data VBA:$42 0–2 ESSI1 Receive Data With Exception Status VBA:$44 0–2 ESSI1 Receive Last Slot VBA:$46 0–2 ESSI1 Transmit Data...
ESSI0 TX Data With Exception Interrupt ESSI0 Transmit Last Slot Interrupt ESSI0 TX Data Interrupt ESSI1 RX Data With Exception Interrupt ESSI1 RX Data Interrupt ESSI1 Receive Last Slot Interrupt ESSI1 TX Data With Exception Interrupt B-10 DSP56303 User’s Manual...
Interrupt Sources and Priorities Table B-4. Interrupt Source Priorities Within an IPL (Continued) Priority Interrupt Source ESSI1 Transmit Last Slot Interrupt ESSI1 TX Data Interrupt SCI Receive Data With Exception Interrupt Lowest SCI Receive Data Highest SCI Transmit Data SCI Idle Line SCI Timer Timer0 Overflow Interrupt Timer0 Compare Interrupt...
Programming Sheets Date: Application: Programmer: Sheet 1 of 3 Bus Interface Unit NOTE: All BCR bits are read/write control bits. Default Area Wait Control, Bits 20–16 Bus Request Hold, Bit 23 Area 3 Wait Control, Bits 15–13 0 = BR pin is asserted only for attempted or pending access Area 2 Wait Control, Bits 12–10 1 = BR pin is always asserted...
Programming Sheets Date: Application: Programmer: Sheet 3 of 3 Bus Interface Unit Bus Packing Enable, Bit 7 0 = Disable internal packing/unpacking logic 1 = Enable internal packing/unpacking logic Bus Y Data Memory Enable, Bit 5 0 = Disable AA pin and logic during external Y data space accesses 1 = Enable AA pin and logic during external Y data space accesses...
HDDS HMUX HASP HDSP HROD HAEN HREN HCSEN HA9EN HA8EN HGEN Host Port Control Register (HPCR) X:$FFFFC4 Read/Write Reset = $00 = Reserved, Program as 0 Figure B-11. Host Base Address and Host Port Control Registers B-22 DSP56303 User’s Manual...
Programming Sheets Date: Application: Programmer: Sheet 5 of 5 HOST Host Side Contains the interrupt vector or number Interrupt Vector Register (IVR) Host Address: $3 Read/Write Reset = $0F Host Transmit Data (usually loaded by program) Transmit Low Byte Transmit Middle Byte Transmit High Byte Not Used Transmit Byte Registers...
X:$FFFFC8 Write Reset = $00 DRx holds value of corresponding HI08 GPIO pin. Function depends on HDDR. Host Data Register (HDR) X:$FFFFC9 Write Reset = Undefined Figure B-23. Host Data Direction and Host Data Registers (HDDR, HDR) B-34 DSP56303 User’s Manual...
Programming Sheets Date: Application: Programmer: Sheet 2 of 4 GPIO Port C (ESSI0) PCn = 1 Port Pin configured as ESSI PCn = 0 Port Pin configured as GPIO PCC5 PCC4 PCC3 PCC2 PCC1 PCC0 Port C Control Register (PCRC) X:$FFFFBF Read/Write Reset = $000000 PDCn = 1...
PDn is reflected on port pin n PDD5 PDD4 PDD3 PDD2 PDD1 PDD0 Port D GPIO Data Register (PDRD) X:$FFFFAD Read/Write Reset = $000000 = Reserved, Program as 0 Figure B-25. Port D Registers (PCRD, PRRD, PDRD) B-36 DSP56303 User’s Manual...
Programming Sheets Date: Application: Programmer: Sheet 4 of 4 GPIO Port E (SCI) PCn = 1 Port Pin configured as ESSI PCn = 0 Port Pin configured as GPIO PCE2 PCE1 PCE0 Port E Control Register (PCRE) X:$FFFF9F Read/Write Reset = $000000 PDCn = 1 Port Pin is Output PDCn = 0...
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8-8 Bus Release Timing (BRT) bit 4-17 program 4-8 Bus Request Hold (BRH) bit 4-26 program options, invoking 4-8 Bus Row Out-of-Page Wait States (BRW) bit 4-29 ROM 1-5 Bus Software Triggered Reset (BSTR) bit 4-28 DSP56303 User’s Manual Index-1...
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Shift Direction (SHFD) 7-22 DSP56300 Synchronous/Asynchronous (SYN) 7-21 core 1-1 Transmit 0 Enable (TE0) 7-20 Family Manual 1-1 Transmit 1 Enable (TE1) 7-21 DSP56303 Transmit 2 Enable (TE2) 7-21 Technical Data 1-1 Transmit Exception Interrupt Enable DSP-to-host (TEIE) 7-19 data word 6-2...
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7-13 Framing Error Flag (FE) bit 8-17 Synchronous Serial Interface Status Register (SSISR) 7-14 7-28 bit definitions 7-28 Receive Data Register Full (RDF) 7-28 general-purpose flags for host-DSP communication 6-7 Receiver Frame Sync Flag (RFS) 7-29 Index-4 DSP56303 User’s Manual...
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General-Purpose Input/Output (GPIO) 1-12 2-20 Host GPIO Port Enable (HGEN) bit 6-20 functions 6-4 Host Interface (HI08) 2-2 2-10 2-11 2-13 2-14 Host Data Direction Register (HDDR) 6-13 6-33 chip-select logic 6-17 Host Data Register (HDR) 6-13 6-33 Command Vector Register (CVR) 6-8 6-23 Port B 5-7 Host Command (HC) 6-27...
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Memory Switch Mode (MS) 4-17 Port C Direction Register (PRRC) 7-37 programming sheet B-13 programming sheet B-35 Port D 2-2 SCS byte 4-15 Stack Extension Enable (SEN) 4-15 control registers 7-36 Stack Extension Overflow Flag (EOV) 4-16 ESSI1 5-8 Stack Extension Underflow Flag (EUN) 4-16 Port D Control Register (PCRD) 7-36 Stack Extension Wrap Flag (WRP) 4-15 programming sheet B-36...
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Transmit Clock Source (TCM) 8-19 Data Word Formats 8-10 SCI Clock Polarity (SCKP) bit 8-12 enable wakeup function 8-15 SCI Control Register (SCR) 8-9 8-12 enable/disable SCI receive data with exception bit definitions 8-12 interrupt 8-12 Index-10 DSP56303 User’s Manual...
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exceptions 8-8 Framing Error Flag (FE) 8-17 Idle Line 8-8 Idle Line Flag (IDLE) 8-18 Overrun Error Flag (OR) 8-18 Receive Data 8-8 Receive Data with Exception Status 8-8 Parity Error (PE) 8-17 Timer 8-9 Receive Data Register Full (RDRF) 8-18 Transmit Data 8-8 Received Bit 8 (R8) 8-17 GPIO 5-9...
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Test Access Port (TAP) 1-5 Timer Compare Interrupt Enable (TCIE) bit 9-32 Time Slot Register (TSR) 7-33 Timer Compare Register (TCPR) 9-4 9-34 timer 2-2 2-20 Timer Control (TC) bits 9-31 after Reset 9-3 Timer Control/Status Register (TCSR) 9-3 9-28 Index-12 DSP56303 User’s Manual...
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bit definitions 9-28 Transmit Slot Mask Registers (TSMA and TSMB) 7-14 Data Input (DI) 9-29 7-33 Transmitter Empty (TRNE) bit 8-18 Data Output (DO) 9-29 Direction (DIR) 9-30 Transmitter Enable (TE) bit 8-14 Inverter (INV) 9-30 9-32 Transmitter Ready (TRDY) bit 6-28 Prescaler Clock Enable (PCE) 9-29 Transmitter Underrun Error Flag (TUE) 7-28 programming sheet B-32...