Flush Operation; Memory Access Mode; Flush Mode - Motorola DSP56305 User Manual

VITERBI CO-PROCESSOR
Operating Modes
13.4.3.3

Flush Operation

In this stage, there are no more symbol inputs and only the remaining bits in the trellis
memory are left to process. The trellis path is selected according to the Flush Control
modes (end_state or best metric). The remaining bits are shifted out and (as in normal
operation) re-encoding and BER calculation is applied.
13.4.4

Memory Access Mode

The Memory Access mode enables the DSP56300 core to write data into SP, VP and the
Metric internal RAMs. The VBER register/counter holds the address of the access while
the data is held in VMEM. During the Memory Access mode every memory write of
VMEM increments the memory address such that the next access is performed at the
consecutive location. When accessing SP and VP RAMs (which are 16-bit wide), full
16-bit data words are written via VMEM.
For the support of differential metric schemes a 24-bit word is used to read/write the
Metric RAM, where the metric data occupies the 22 least significant bits, zero extended
The address value in the Metric RAM represents the state value, e.g. reading the content
of address #J in the Metric RAM gives the Path Metric value of state #J. A sequential read
of the Metric RAM contents gives the Path Metric values from state #0 to state #(n–1)
sequentially. Refer to memory access examples in Section 13.9.3, and see Section 13.7 for
a detailed description on the trellis state formation.
13.4.5

Flush Mode

During both equalization and decoding modes, the Flush mode is enabled automatically
by VCOP after the completion of an input block of data when the VCNT register reaches
zero. In this mode the remaining bits in the trellis RAM are shifted out and processed
(i.e. BER computation for channel decoding). The desired trellis-path is selected
according to the Flush Control modes – ending state or best metric. At the end of the
flush process the VCOP returns to idle state. The Flush mode can also be invoked
explicitly during decoding or equalization by clearing DECEN or EQEN and setting the
FLEN bit in VCRA. In this case the VCOP will suspend the current processing and start
the flush operation as described above.
13-14 DSP56305 User's Manual
3
.
MOTOROLA