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GE Intelligent Platforms – CM6 Hardware Reference Manual, Fourth Edition
Table 24: Reset sources
Source
Power Monitor
Reset Button
Reset from COP Interface
Host Reset
Watchdog Reset
PMC Reset
cPCI Reset
Description
All voltages are monitored and if one voltage
is below the minimum requirement the CM6
is hold in reset.
External reset button connected at PRST#
(cPCI-J2 pin C17). A low signal will issue a
board reset. The PRST# is also active if the
CM6 is in peripheral mode this deviants from
the cPCI specification.
The board can be reset from the COP debug
tool via COP_HRST# (cPCI-J2 pin E16).
The CPU may request a reset, signal is
controlled by software.
If the two stage watchdog time is elapsed the
watchdog requests a reset.
A Non-Monarch PMC (monarch is not
supported) processor board may hold the
CM6 and all subsystems in reset if this signal
is active (RSTOUT# at PMC_Jn2 pin 59).
The compact PCI reset (cPI_J1 pin C5) is a
bi-directional signal. In system mode the
signal is the output of the internal reset and
the reset source for all peripheral boards and
subsystems at the cPCI system.
In non-system mode it is an input and holds
the CM6 (as cPCI peripheral) in reset.
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