GE CM6 Hardware Reference Manual page 51

GE Intelligent Platforms – CM6 Hardware Reference Manual, Fourth Edition
The implemented watchdog has two timer stages the watchdog interrupt
(WINT) and the watchdog reset (WRST). The elapsing of the first timer stage
(WINT) generates a System Management Interrupt (SMI), and starts the second
stage (WRST) of the watchdog and may generate a reset if the selected time of
the second stage is elapsed.
The watchdog timers are retriggered by a write to register WTIG and will reset
both watchdog stages (WINT and WRST).
The watchdog is disabled if WINT[2:0] = 000. If WRST[2:0] = 000 the reset
will be generated at the elapsing time of the WINT watchdog timer.
After power-on the watchdog is active and will perform a reset after 256ms, if
no retrigger or disable command is performed.
It is possible to write protect (WDG_WP bit in the Control Register) the
Watchdog register (WCR) to prevent unallowed writes.
Watchdog Trigger (WTIG)
Address: Base + Offset 5
Size: 8 bit
Table 14: Watchdog Trigger (WTIG)
Bit Name Write
7-0 WTIG Retrigger watchdog
timer
Any write to this register will reset the Watchdog timers and restart the timers
with the selected watchdog time.
Boot Code Register (BCR)
Address: Base + Offset 6
Size: 8 bit
Table 15: Boot Code Register (PCR)
Bit Name Write
7-0 PCODE Boot Code
It is possible to write Boot Codes to this register. If this Boot Code has another
value than '00hex' and longer stable than two seconds the value is transferred
to the red LED (morse code). A long blink is a 1; short blink is 0 starting with
bit seven of the actual Boot Code.
PLD Version Register (VER)
Address: Base + Offset 7
Size: 8 bit
Table 16: PLD Version Register (VER)
Bit Name Write
7-0 PLD N/a
Read Default
Always 0 -
Read Default
Last Boot code 0x00
Read Default
PLD Version -
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