GE CM6 Hardware Reference Manual page 60

Serial Interface
Ethernet Interface
GE Intelligent Platforms – CM6 Hardware Reference Manual, Fourth Edition
No backup operation during power-off time is provided to the Real Time
Clock, so each time the board is switched on the actual date/time must be
reloaded by software.
External Write Protection
The HW_WP# signal at the backplane (J2 pin D21) prevents any write to the
nvSRAM/RTC. If the HW_WP# signal is asserted (active low) all write
commands to the nvSRAM/RTC device are disabled. That means also the RTC
part is write protected. The state of HW_WP# can be read in the CPLD Status
Register0 bit 4.
Device Write Protect
Inside the MPC8641 Local Bus Controller register set the according chip select
(LCS2) of the Flash Device may set to write protect.
The CM6 has two serial ports which are provided by the MPC8641 DUART.
The DUART consists of two universal asynchronous receiver/transmitters
(UARTs). Each UART is clocked by the MPX bus clock. The DUART
programming model is compatible with the PC16552D.
The DUART includes these features:
• Full-duplex operation
• Programming model compatible with the original PC16450 UART and the
PC16550D (an improved version of the PC16450 that also operates in FIFO
mode)
• FIFO mode for both transmitter and receiver, providing 16-byte FIFOs
• Serial data encapsulation and decapsulation with standard asynchronous
communication bits (START, STOP, and parity)
• Maskable transmit, receive, line status, and modem status interrupts
• Software-programmable baud generators that divide the MPX clock by 1 to
16
(2 – 1)
• Clear to send (CTS) and ready to send (RTS) modem control functions
• Line and modem status registers
• Line-break detection and generation
• Internal diagnostic support, local loopback, and break functions
• Prioritized interrupt reporting
• Overrun, parity, and framing error detection
The COM1 Port at the CM6 has a RS232 compliant driver and the COM2 Port
a RS422/485 compliant driver. The RS422/485 driver outputs can be controlled
by a driver enable signal from the CPLD Control Register (CR)
bit 0.
The MPC8641 provides four Ethernet controllers; two of them are used in the
CM6. Each channel has a reduced Gigabit Media Independent Interface
(RGMII) interface to communicate with the Gigabit Phy MV88E1118. The two
physical interface controllers provide the 10/100/1000 Base-T Ethernet to rear
cPCI_J2 connector.
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